Wave transmission lines and networks – Coupling networks – With impedance matching
Reexamination Certificate
2001-06-27
2003-03-11
Jones, Stephen (Department: 2817)
Wave transmission lines and networks
Coupling networks
With impedance matching
C333S238000
Reexamination Certificate
active
06531932
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to flip chip packages, and more particularly to the design of a trace layout in a flip chip package to optimize signal line impedance control.
BACKGROUND OF THE INVENTION
FIG. 1A
is a cross sectional view showing the layer stack up of a typical microstrip 4-layer flip chip package substrate. The substrate
12
is typically a printed circuit board or the like. Layer
1
of the substrate
12
located on the top of the substrate
12
and is a top signal layer
14
, and layer
2
, is a ground plane (Vss)
16
. Layer
3
is a power plane (Vdd)
18
, and layer
4
is a bottom signal layer
20
. As shown in
FIG. 1B
illustrating a top view of the 4-layer flip-chip substrate
12
, a pattern of signal traces
30
are patterned on the top signal layer
14
. Referring again to
FIG. 1A
, a die
22
is connected to the signal traces
30
on the top signal layer
14
by way of solder bumps
24
. Although not illustrated, the bottom signal layer
20
may also include a pattern of signal traces that are also connected to the solder bumps on the die
22
through vias (not shown).
Microstrip constructions in which the signal traces
30
of one layer can only reference one plane, as shown in
FIGS. 1A and 1B
, are susceptible to noise. Noise can be caused by several sources. For example, as high speed signals pass through each signal trace
30
, field lines are generated around the signal traces
30
that cause cross talk among adjacent traces
30
. Another source of noise includes signal reflections from discontinuities in the package and board during signal transmission. Such discontinuities are more in a microstrip substrate since the traces
30
on the top layer may be affected by the assembly materials such as the stiffener used. A metallic stiffener can act as a floating plane and cause impedance variation in the traces
30
.
Because the efficiency at which signals are shielded from noise and discontinuities in the signal transmission is inadequate in microstrip constructions, microstrip flip-chip packages are unsuitable for applications having critical signal I/O's that require precise impedance control and minimum noise.
One method for minimizing noise is to use stripline construction for the package substrate.
FIG. 1C
is a cross sectional view showing the layer stack up of a conventional stripline 6-layer flip-chip package substrate. Stripline construction minimizes noise because additional layers are included for carrying power and ground planes
16
′ and
18
′, which sandwich the signals
14
′ and
20
′ between power and ground planes
16
′ and
18
′. Although stripline construction is more effective at reducing noise than microstrip construction, stripline construction cost more due to the additional layers.
Accordingly, what is needed a method for fabricating a microstrip package that achieves a precise characteristic impedance required for specialized signal I/O's and optimum noise shielding and at low cost without adding additional layers. The present invention addresses such a need.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a microstrip package to optimize signal trace impedance control and cross talk noise shielding. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.
According to the system and method disclosed herein, the present invention achieves a precise characteristic impedance required for specialized signal IO's and optimum noise shielding without adding additional layers and at low cost.
REFERENCES:
patent: 3593174 (1971-07-01), White
patent: 4362899 (1982-12-01), Borrill
patent: 5376588 (1994-12-01), Pendse
patent: 5696027 (1997-12-01), Crane, Jr.
patent: 5952726 (1999-09-01), Liang
patent: 6048753 (2000-04-01), Farnworth
patent: 6064113 (2000-05-01), Kirkman
patent: 6111756 (2000-08-01), Moresco
patent: 6198635 (2001-03-01), Shenoy et al.
“Direct Rambus ASIC Package Selection Guide Version 0.1”, Nov. 1999, Rambus Inc.
Ghahghahi Farshad
Govind Anand
Thurairajaratnam Aritharan
Jones Stephen
Sawyer Law Group LLP
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