Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material
Reexamination Certificate
2001-06-07
2003-04-08
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Non-single crystal, or recrystallized, semiconductor...
Amorphous semiconductor material
C257S072000, C257S347000, C349S043000
Reexamination Certificate
active
06545293
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a thin film transistor (TFT). In particular, the present invention relates to a TFT-liquid crystal display (LCD).
2. Description of the Related Art
Currently, a liquid crystal display (LCD) with the advantages of low power consumption, thin thickness, light weight, and low driving voltage, has been put to these practical use, such as personal computers, navigation systems, Gameboys, projectors, view finders and portable machines (watches, electronic calculators, and televisions).
An electric field is applied on the LCD to change the alignment of the liquid crystal (LC) molecules and transmit light through the LC molecules to display images. A TFT-LCD is to use a thin film transistor (TFT) as a switch device, and has the advantages of low power consumption, lightweight, and low driving voltage. However, since the TFT is thinner than traditional transistors, there are seven photolithography steps in the manufacturing process of the TFT resulting in poor yield and high cost. In order to improve the above-mentioned problems, it is needed to develop a manufacturing method for reducing the number of the photolithography process.
U.S. Pat. No. 5,478,766 disclosed a process for forming a TFT-LCD by using at least four photolithography processes. Referring to FIG.
1
and
FIG. 2
,
FIGS. 1A
to
1
C show top views of the masks in the process, and
FIGS. 2A
to
2
E are the cross-sectional diagrams along the line
2
-
2
′ in
FIG. 1
according to the prior art. First, as shown in FIG.
1
A and
FIG. 2A
, a first metal layer is deposited and patterned on a substrate
21
for forming a gate electrode
22
and a gate line connected to the gate electrode
22
by a first photolithography process. Further, a gate insulating layer
23
is covered on the gate electrode
22
. Then, as shown in
FIG. 2B
, an insulating layer
24
, an amorphous silicon (a-Si) layer
25
, and a doped silicon layer
26
are deposited on the substrate
21
. As shown in
FIGS. 1B and 2C
, a second metal layer is further deposited on the doped silicon layer
26
. The second metal layer is then patterned to form a signal line
27
and a source/drain metal layer
28
by a second photolithography process. Referring to
FIGS. 1C and 2D
, an indium tin oxide (ITO) layer is deposited and patterned on the substrate
21
by performing a third photolithography process. The ITO layer includes a signal line area
29
and a pixel area
30
. Finally, a fourth photolithography process is performed to remove parts of the source/drain metal layer
28
and the doped silicon layer
26
which are not covered by the ITO layer. Accordingly, as shown in
FIG. 2E
, the remaining second metal layer and amorphous silicon layer
26
respectively form a source electrode
31
, a drain electrode
32
, and a contact layer
33
.
According to the above-mentioned process, the 4-mask photolithography process can improve the yield and reduce the cost. However, the first metal layer is not connected to the second metal layer in the prior art. That is, a protecting circuit is not formed to avoid the damage of electrostatic discharge (ESD) in the prior art. Thus, how to avoid the ESD effect becomes an important issue.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a thin film transistor (TFT) flat display and a method of making the same in order to solve the above-mentioned disadvantages.
The TFT display in the present invention includes a substrate having at least a transistor area and a bonding pad area, and a gate electrode and a gate pad respectively formed in the transistor area and the bonding pad area. The gate pad has a first area and a second area. The display further includes an insulating layer formed on the substrate to cover the gate electrode and the first area of the gate pad, a first semiconductor layer covering the insulating layer, a second semiconductor layer covering a predetermined area of the first semiconductor layer, and a metal layer covering the second semiconductor layer to form a source electrode and a drain electrode. A channel forms between the source electrode and the drain electrode. The display also includes a first conductive layer formed on the drain electrode, the source electrode, and the substrate except for the surface of the gate pad, a protective layer formed on the transistor area and the bonding pad area, and a second conductive layer formed on the area uncovered by the protective layer and the second area of the gate pad. The protecting layer fills in the channel and covers the first conductive layer above the source electrode, the drain electrode, and the first are of the fate pad. Further, the second conductive layer connects to the first conductive layer for electrically connecting the gate pad and the metal layer.
It is an advantage of the present invention that the TFT display can provide a protective circuit for preventing the ESD effect.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5478766 (1995-12-01), Park et al.
patent: 5731856 (1998-03-01), Kim et al.
patent: 5825449 (1998-10-01), Shin
patent: 5867242 (1999-02-01), Yao et al.
patent: 5990986 (1999-11-01), Song et al.
patent: 6338989 (2002-01-01), Ahn et al.
patent: 6339230 (2002-01-01), Lee et al.
patent: 2002/0048866 (2002-04-01), Wong
patent: 9-189924 (1997-07-01), None
AU Optronics Corp.
Flynn Nathan J.
Sefer Ahmed N.
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