Semiconductor integrated circuit having logic circuit...

Details Semiconductor integrated circuit having logic circuit... Semiconductor integrated circuit having logic circuit...

2000-12-19

2003-04-08

Nelms, David (Department: 2818)

Static information storage and retrieval

Format or disposition of elements

C365S063000, C365S230060, C326S106000

Reexamination Certificate

active

06545892

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, to the structure and pattern layout of a logic circuit which is preferably applied to a decoder circuit of semiconductor memory devices or the like.
2. Description of the Related Art
Conventional decode circuits in semiconductor memory devices have the function of selecting a specific address in a memory cell, and the decoder circuits generally employ, for example, a two-input NAND circuit explained below.
FIG. 12
is a circuit diagram showing an example of such a NAND circuit.
The shown NAND circuit
100
consists of a logic section
101
using CMOS transistors, and an output section
102
using bipolar and MOS transistors.
The logic section
101
includes a parallel-connected circuit employing two pMOS (i.e., p-channel MOS) transistors M
51
and M
52
, and a serially connected circuit employing two nMOS (i.e., n-channel MOS) transistors M
53
and M
54
. The parallel-connected circuit and the serially-connected circuit are farther serially connected in this order between a high-potential power supply line
103
(i.e., voltage=Vcc) and an earth (or grounding) line
104
.
Among two input signals A and B to be logically operated, signal A is input into the gate electrodes of pMOS transistor M
51
and nMOS transistor M
53
, while signal B is input into the gate electrodes of pMOS transistor M
52
and nMOS transistor M
54
. A signal resulting from this operation is output from a common drain electrode of pMOS transistors M
51
and M
52
, and nMOS transistors M
53
and M
54
to output section
102
.
In the output section
102
, bipolar transistor (abbreviated to “BiP-Tr”, hereinafter) Q
1
whose collector electrode is connected to the power supply line
105
, and two nMOS transistors M
55
and M
56
are serially connected in this order between the power supply line
105
and earth line
106
, as shown in
FIG. 12. A
logic signal from logic section
101
is input into the base electrode of BiP-Tr Q
1
, and input signals A and B are respectively input into the gate electrodes of the nMOS transistors M
55
and M
56
. This two-input Bi-CMOS NAND circuit uses the contact of the drain electrode of the nMOS transistor M
55
and the emitter electrode of the BiP-Tr Q
1
in the output section as an output terminal from which output signal X
0
is output.
In the NAND circuit
100
as shown in
FIG. 12
, when both signals A and B are high, the serially connected nMOS transistors M
53
and M
54
are on (i.e., in the ON states), while the parallel-connected pMOS transistors M
51
and M
52
are off (i.e., in the OFF states). As a result, the electric potential of the base electrode of the BiP-Tr Q
1
becomes ground level, so that the transistor is set to the OFF state. In addition, the serially connected nMOS transistors M
55
and M
56
are switched on, so that the electric charges of a load (not shown) are discharged via these transistors M
55
and M
56
, and the level of the output signal X
0
becomes low.
In contrast, when signal A or B is low, one of the nMOS transistors M
53
and M
54
is off; thus, these nMOS transistors M
53
and M
54
have no effect on the decrease of the base potential of the BiP-Tr Q
1
. Here, one of the pMOS transistors M
51
and M
52
is on; therefore, the above pMOS transistors M
51
and M
52
increase the electric potential of the base of the BiP-Tr Q
1
. As a result, the voltage at the base of the BiP-Tr Q
1
is increased to Vcc, and the transistor is switched on. On the other hand, one of the serially connected nMOS transistors M
55
and M
56
is switched off, so that these transistors have no effect on the discharge from the output terminal. As a result, according to the charging operation using the BiP-Tr Q
1
, the level of the output signal X
0
becomes high.
That is, the output from circuit
100
as shown in
FIG. 12
is low only when both of the two inputs are high, and in other cases, the output is high based on the NAND logic. Decoder circuits provided in semiconductor storage devices or the like often employ logic circuits as explained above. Here, a feature of the circuit operation is that only one of arrayed NAND gates outputs a low level signal (i.e., LOW signal) as a selected output, and the others output high level signals (i.e., HIGH signals) as non-selected outputs. In the decoder circuit, a plurality of such gate structures are connected, and the memory cell designated by an input address can be selected.
In the above conventional NAND circuit, the level of the output signal can be made high by using the BiP-Tr Q
1
to which the base current is supplied using the pMOS transistors M
51
and M
52
. Therefore, sufficient current can be supplied, and the operation speed can be high. However, the level of the output signal can be made low by (i) decreasing the potential of the base of the BiP-Tr Q
1
by using the serially connected nMOS transistors M
53
and M
54
, and (ii) drawing electric charges (i.e., current) from an output load by using the serially connected nMOS transistors M
55
and M
56
. This means that in the nMOS transistor, the equivalent gate length is double while the current supplying ability is half, compared with the other cases.
In order to compensate for the reduction (by half) of the current supplying ability, generally, the gate width of the nMOS transistor is designed to be wider so as to improve the current supplying ability and to prevent a delay in the speed of the drop in potential. However, the increase of the gate width causes an increase of the input capacitance observed from the input signal side; thus, the operation speed of the logic circuit as the former stage is decreased. That is, in order to improve the operation speed of a circuit having a plurality of logic gates, it is necessary to improve the fan-out characteristics (i.e., the relationship between the ratio of the capacitance of the output (load) to the capacitance of the input, and the delay time). However, the degradation of the current supplying ability of the serially connected nMOS transistors is an obstacle which must be overcome to improve the fan-out characteristics. In addition, the increase of the gate width obviously causes an increase of the area of the logic circuit.
As for the decoder circuit, the speed of the selecting operation, which is a characteristic operation of this circuit, depends on the delay time of the output selected signal. Here, the selecting operation is performed by decreasing the output level by using serially connected nMOS transistors (or by increasing the output level by using serially connected pMOS transistors in case of a NOR circuit). Therefore, the decrease of the current supplying ability with respect to the serially connected MOS transistors has a considerable effect on the operation speed.
In order to solve the operational delay, increase of the occupied area, and the like in such logic circuits, the inventors of the present invention proposed the logic circuit, having a structure as shown in
FIGS. 13 and 14
, which is disclosed in Japanese Unexamined Patent Application, First Publication, No. Hei 9-200036.
In the conventional circuit shown in
FIG. 12
, each of the current path for decreasing the potential of the base of the BiP-Tr Q
1
and the current path for drawing electric charges from an output load is formed using two serially connected nMOS transistors. In contrast, the circuit
200
in
FIG. 13
, each path (here, the BiP-Tr Q
2
is used) is formed using a single nMOS transistor M
63
or M
64
. Among two input signals A and B, ∇B (here, ∇ represents an upper bar indicating inversion, hereinafter), the inverted signal of input signal B, is input into the source electrodes of the nMOS transistors M
63
and M
64
. The same logic as that realized in the circuit shown in
FIG. 12
can also be realized in the circuit
200
. In the structure of circuit
200
, the input capacitance is half as much as that of the conventional gate-input capacitance, and the

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