Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-12-11

2003-09-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233500, C365S194000, C365S189050

Reexamination Certificate

active

06618320

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a semiconductor memory device that contains two double data rate (DDR) type dynamic random access memories (DRAMs) (DDR-DRAMS) in one package and the data input/output lines of the two DDR-DRAMs are commonly connected.
BACKGROUND ART
Recently, semiconductor memory devices, among which a DRAM is typical, are required to have an improved data transfer rate as well as to have an increased data capacity. To meet the demand, various new types of DRAMs, such as a synchronous DRAM that can realize a high data transfer rate, have been proposed. In an SDRAM, internal operations are carried out in synchronization with an external clock in a pipeline method, and data input/output are also carried out in synchronization with the external clock. It is, therefore, necessary to provide an external clock to an SDRAM.
In a conventional SDRAM, data is transferred in synchronization with the leading edge of a clock and, therefore, the data transferring cycle is the same as the clock cycle. Contrary to this, a double data rate (DDR) type DRAM (DDR-RAM) has been proposed, in which data can be transferred at double the rate compared to a conventional type, provided the same clock cycle is used, by transferring data in synchronization with both the leading edge and the trailing edge of the clock.
FIG. 1
is a block diagram that shows the basic structure of a DDR-DRAM. An external clock generation circuit
11
generates an internal clock ICLK or an output clock OCLK, and signals such as input timing signals with which address signals and control signals are read, from complementary clocks CLK and /CLK, and a clock enable signal CKE entered from the outside. A command decoder
12
receives and decodes control signals such as /CS, /RAS, /CAS, /WE and AP in synchronization with the input timing signals and supplies the decoded results to control signal latches
15
-A, B, C and D, a mode register
16
, and a data input/output portion
14
. An address buffer
13
receives address signals A
0
to A
11
and bank select signals BA
0
and BA
1
and supplies them to the control signal latches
15
-A, B, C and D, the mode register
16
and column address counters
17
-A, B, C and D and at the same time supplies row addresses to DRAM cores
18
-A, B, C and D. In the write mode, the data input/output portion
14
receives data DQ
0
to n in synchronization with a data input/output timing signal DQS and supplies it to the DRAM cores
18
-A, B, C and D. In the read mode, it outputs the data read from the DRAM cores
18
-A, B, C and D as the data DQ
0
to n in synchronization with the output timing signal. The output timing signal is output as the data input/output timing signal DQS.
Among the control signal latches
15
-A, B, C and D, the circuit that corresponds to the bank select signal from the address buffer
13
latches the control signal from the command decoder
12
and outputs RAS, CAS and WE to the corresponding DRAM core among.
18
-A, B, C and D. The mode register
16
controls so that column addresses that correspond to the column address counters
17
-A, B, C and D are set in accordance with the mode specified according to the control signal from the command decoder
12
and the signal from the address buffer
13
. The column address counters
17
-A, B, C and D output column addresses, the number of which is equal to that of the addresses specified by the set column addresses, to the DRAM cores
18
-A, B, C and D sequentially. The DRAM cores
18
-A, B, C and D shown schematically have a four-bank structure and an activated bank writes the write data to be supplied to I/O in accordance with the control signals RAS, CAS, WE, the row address and the column address into the memory cell of the specified address in the write mode, and in the read mode, it supplies the data read from the memory address of the specified address to I/O. In an SDRAM such as a DDR-DRAM, as plural banks are accessed alternately, when data is read at, for example, 200 MHz, data is read from each bank at 100 MHZ and only the output section outputs data at 200 MHz.
As the DDR-DRAM is widely known, a further description is not given here. In the following description, although the output action of the read data is mainly described, the data write action can be described in the same way.
FIG. 2
is a time chart that shows the action in the data read mode in a conventional DDR-DRAM. As shown schematically, when it receives CLK indicated by the solid line and its complementary signal /CLK indicated by the dashed line as external signals, and a read command, the DDR-DRAM outputs first data Q
1
in synchronization with the leading edge of CLK and outputs second data Q
2
in synchronization with the leading edge of /CLK a half cycle behind, that is, the trailing edge of CLK. The two items of data Q
1
and Q
2
are, therefore, read during a cycle of the external clock CLK. Only one item of data was output during a cycle of the external clock CLK in synchronization with only the leading edge of the external clock CLK in the past, but if the cycle is the same as that of the external clock, it is possible for the DDR-DRAM to read twice as much data as a conventional SDRAM.
In the case of the data write action of the DDR-DRAM, as the write data changes in synchronization with the leading edge and trailing edge of the external clock CLK, the data is latched at a point where the write data becomes stable, for example, at a point a quarter cycle shifted from the leading edge or the trailing edge.
As described above, the DDR-DRAM is able to transfer data at double the conventional rate, provided the clock cycle is the same, but it is necessary to increase the speed of the clock and the internal action in order to further increase the data transfer rate. For example, if data is transferred at a frequency of 400 MHz, it is necessary to use a clock of 200 MHZ and each bank within the DRAM is required to operate at 200 MHz, even if the DDR method is adopted. A higher speed of a memory device has been achieved by reducing the design rule, the wiring resistance, the number of circuit stages, etc., but a physical limit relating to the electron speed or the like is close and it will be difficult to achieve a still higher speed by improving the conventional technologies for reducing the design rule, the wiring resistance, etc.
DISCLOSURE OF INVENTION
The present invention has been developed in order to break through the above-mentioned circumstances and the object of the present invention is to realize a semiconductor memory device that can increase only the data transfer rate while the clock speed and the internal action speed of a DDR-DRAM remain unchanged.
In order to realize the above-mentioned object, the semiconductor memory device of the present invention comprises two DDR-DRAMs within one package, which are commonly connected to data input/output lines, resulting in being integrated into one semiconductor memory device. Moreover, the semiconductor memory device is provided with a clock generation circuit that generates from external clocks a first clock whose frequency and phase are the same as those of the external clocks and a second clock whose frequency is the same as that of the external clocks but phase is shifted by a quarter phase, and the first clock and the second clock are supplied to the two DDR-DRAMs as clocks. As a result, the two DDR-DRAMs operate in a state of being a quarter phase shifted from each other. If the data output from each DDR-DRAM continues for a half cycle, a problem occurs that the outputs of the data from the two DDR-DRAMs overlap each other. In order to avoid this problem, the data output portion of the first DDR-DRAM outputs data for the time periods corresponding to a quarter phase from points a fixed phase behind the leading edge and the trailing edge, respectively, of the first clock, and the data output circuit is kept in a high impedance state for other time periods, and the data

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