Liquid crystal cells – elements and systems – Nominal manufacturing methods or post manufacturing...
Reexamination Certificate
2000-09-13
2003-05-20
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Nominal manufacturing methods or post manufacturing...
C349S044000, C349S111000
Reexamination Certificate
active
06567151
ABSTRACT:
CROSS REFERENCE
This application claims the benefit of Korean Patent Application No. 1999-38974, filed on Sep. 13, 1999, under 35 U.S.C. § 119, the entirety of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and a method of manufacturing the same.
2. Description of Related Art
A typical LCD device includes lower and upper substrates with a liquid crystal layer interposed therebetween. The lower substrate has a thin film transistor (TFT) as a switching element and a pixel electrode, and the upper substrate has a color filter and a common electrode. The pixel electrode serves to apply a voltage to the liquid crystal layer in conjunction with the common electrode, and the color filter serves to implement natural colors.
FIG. 1
is a plan view illustrating a lower array substrate of the conventional LCD device. As shown in
FIG. 1
, the lower array substrate includes gate lines
60
arranged in a transverse direction, data lines
70
arranged in a longitudinal direction, TFTs arranged near the cross point of the gate and data lines
60
and
70
, and pixel electrodes
40
arranged on a region defined by the gate and data lines
60
and
70
. Each of the TFTs includes a gate electrode
60
a
, a source electrode
70
a
, a drain electrode
70
b
, and a semiconductor layer
80
. The gate electrode
60
a
extends from the gate line
60
, and the source electrode
70
a
extends from the data line
70
. The drain electrode
70
b
is laterally spaced from the source electrode
70
a
and is electrically connected with the pixel electrode
40
through a contact hole
90
. A portion
35
of the pixel electrode
40
overlaps over the gate line
60
, so that a storage capacitor is formed.
FIG. 2
is a cross sectional view taken along line II—II of FIG.
1
. As shown in
FIG. 2
, the gate electrode
60
a
is formed on the substrate
100
. The gate electrode
60
a
is made of a metal such as Al, Mo and Cr. A gate insulating layer
30
is formed on the exposed surface of the substrate
100
while covering the gate electrode
60
a
. The semiconductor layer
80
is formed over the gate electrode
60
a
. The semiconductor layer
80
is made of an amorphous silicon. An ohmic contact layer
81
which is ion-doped by impurities is formed on the semiconductor layer, and a portion of the ohmic contact layer
81
over the gate electrode
60
a
is removed. The source and drain electrodes
70
a
and
70
b
overlay the ohmic contact layer
81
at both end portions of the semiconductor layer
80
. A passivation film
50
is formed over the whole surface of the substrate while covering the source and drain electrodes
70
a
and
70
b
. The passivation film
50
has the contact hole
90
therein to expose a predetermined portion of the drain electrode
70
b
. The pixel electrode
40
is formed on the passivation film
50
and is electrically connected with the drain electrode
70
b
through the contact hole
90
.
FIG. 3
is a cross sectional view taken along line III—III of FIG.
1
. As shown in
FIG. 3
, the two adjacent pixel electrodes
40
are spaced apart from each other, and the passivation film
50
is interposed between the data line
70
and the pixel electrodes
40
. Also, the pixel electrodes
40
are horizontally spaced apart from the data line
70
. A black matrix (not shown) is arranged on the upper substrate to cover a space between the data line
70
and the pixel electrode
40
, so that light leakage is prevented. Parasitic capacitors cd
1
and cd
2
are formed between the data line
70
and the two adjacent pixel electrodes
40
. The capacitance of the parasitic capacitors cd
1
and cd
2
increases as a distance between the data line
70
and the pixel electrode
40
becomes smaller. Due to the parasitic capacitors, voltages applied to the data line
70
are distorted and cross talk occurs, leading to poor display quality. Decreasing the parasitic capacitance by lengthening the distance between the data line and the pixel electrode results in a lower aperture ratio.
For the foregoing reasons, there is a need for a liquid crystal display device that can decrease the effects of a parasitic capacitance formed between a data line and a pixel electrode and thereby improve an aperture ratio and a display quality.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a liquid crystal display device having a high aperture ratio and a high display quality.
For example, a preferred embodiment of the present invention provides a liquid crystal display device, including an upper substrate having a color filter and a black matrix; a lower substrate having: a gate insulating layer formed thereon, a data line formed on the gate insulating layer, a light shielding pattern formed on the gate insulating layer and spaced apart from the data line, a passivation film formed over the gate insulating layer, the data line, and the light shielding pattern, and a pixel electrode formed on the passivation film and overlapping a portion of the light shielding pattern; and a liquid crystal layer interposed between the upper and lower substrates.
As a further example, another embodiment of the present invention provides a method of manufacturing a liquid crystal display device, including forming a gate insulating layer on a substrate; depositing a metal layer on the gate insulating layer; patterning the metal layer to form a data line and a light shielding pattern spaced apart from the data line; forming a passivation film over the gate insulating layer, the data line, and the light shielding pattern; and forming a pixel electrode on the passivation film, the pixel electrode overlapping a portion of the light shielding pattern.
The present invention, among other things, advantageously lowers the parasitic capacitance between the data line and the pixel electrode, thereby bringing about a high display quality and a high aperture ratio.
REFERENCES:
patent: 5946060 (1999-08-01), Nishiki et al.
patent: 6356319 (2002-03-01), Park et al.
Akkapeddi P. R.
Birch Stewart Kolasch & Birch, LLP.
Kim Robert H.
LG. Philips LCD Co. Ltd.
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