Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1999-12-29
2003-09-30
Kizou, Hassan (Department: 2662)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
Reexamination Certificate
active
06628679
ABSTRACT:
FIELD
The present invention relates to a SERDES (serializer/deserializer) time domain multiplexing/demultiplexing technique, and more particularly, to a SERDES time domain multiplexing/demultiplexing technique which utilizes circular buffers for multiplexing and demultiplexing and time alignment functions.
BACKGROUND
At present, popularly used time domain multiplexers operate so as to multiplex serial data stream signals which are aligned in phase. That is, these time domain multiplexers do not allow for clock skew which makes them unusable where it is desired to time domain multiplex two or more serial data stream signals which are not aligned in phase.
Similarly, time domain demultiplexers do not allow for demultiplexing one serial data stream signal into two or more serial data stream signals which are not aligned in phase.
SUMMARY
A time domain multiplexing/demultiplexing technique multiplexes N input signals into a single output signal, N being an integer greater than 1, and vice versa. N input signals and N clocks are respectively received and the N input signals are then stored in N respective latches in accordance with the N respective clocks. Outputs of the N latches are sequentially stored in N circular buffers in accordance with the N respective clocks. Outputs from the N circuital buffers are respectively outputted into a multiplexer in accordance with N respective system clocks. One of the respective outputs of the N circular buffers is selectively output to an output latch in accordance with a multiplexer clock input, the output latch latching the output of the multiplexer in accordance with another system clock having a frequency which is N times that of the N input clocks, an output of the output latch providing a time domain multiplexed signal corresponding to the N input signal. A divider outputs an output clock in response to the another system clock.
REFERENCES:
patent: 4759014 (1988-07-01), Decker et al.
patent: 5231636 (1993-07-01), Rasmussen
patent: 5398241 (1995-03-01), Witchey
patent: 5563885 (1996-10-01), Witchey
patent: 5828256 (1998-10-01), Kurisu
patent: 5892920 (1999-04-01), Arvidsson et al.
patent: 5940456 (1999-08-01), Chen et al.
Chen Loop-free asynchronous data sharing in multiprocessor real-time systems based on timing properties. Real time computing systems and applications, 1999. RTCSA '99. Sixth International conference, 1999, pp. 236-246.
LandOfFree
SERDES (serializer/deserializer) time domain... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SERDES (serializer/deserializer) time domain..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SERDES (serializer/deserializer) time domain... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3043561