Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
2001-02-13
2003-07-15
Niebling, John F. (Department: 2812)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C716S030000
Reexamination Certificate
active
06594625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor modeling method for modeling impurity diffusion in a semiconductor, and a reverse short channel effect (RSCE) of a threshold voltage of a MOS field effect transistor (MOSFET). This application is a counterpart application of Japanese application Serial Number 084716/2000, filed Mar. 22, 2000, the subject matter of which is incorporated herein by reference.
2. Description of Related Art
As shown
FIG. 13
, the conventional model representing impurity diffusion in a semiconductor can be classified into the following two types of models. One is a model (hereinafter referred to as Fair model) obtained by setting a target region for analysis, and finding the solution to a diffusion equation for respective impurities, thereby calculating impurity distribution in the semiconductor. The other is a model (hereinafter referred to as Pair Diffusion Model) obtained by setting a target region for analysis, and finding the solution to a diffusion equation for respective point defects themselves and respective impurity-point defect pairs, on the assumption that the respective point defects and the respective impurities form pairs and are diffused, thereby calculating impurity distribution in the semiconductor.
The Fair model has an advantage in that since the number of equations to be solved is only a few, it takes less time in calculation, so that results of a semiconductor simulation can be obtained in a short time. In this case, however, the effect of the point defects on impurity diffusion is not reflected in the diffusion equation, and the same is coped with by increasing or decreasing model parameters such as the diffusion constant, and so forth, and consequently, there has been a risk of simulation precision undergoing deterioration in case that the effect of the point defects on impurity diffusion is significant.
On the other hand, the Pair Diffusion Model has an advantage in that since the effect of the point defects on impurity diffusion is fully taken into account, simulation with high-precision can be achieved, however, this model has had a drawback in that a longer time is required for calculation because the number of equations to be solved increases according as the number of impurities increases.
Owing to such characteristics of the respective models, it has been a general practice to choose the Fair model in the case where a simulation with a predetermined precision can be anticipated by adjusting model parameters, and to choose the pair diffusion model in all other cases.
Now, the mechanism of impurity diffusion in the case where excessive point defects exist in a semiconductor is described hereinafter with reference to FIG.
14
. Excessive point defects occur mainly during a step of ion implantation with a high dose. In particular, excessive point defects occurring in a step of source/drain (S/D) ion implantation into a MOSFET end up pairing up with respective impurities by heat treatment applied immediately thereafter. The respective impurity-point defect pairs are diffused while repeating separation and recombination. Since the point defects cease to exist upon reaching the Si/SiO
2
interface, the impurities pairing up therewith are deposited (piled up) on the spot.
FIG. 15
shows relationships between distance in the longitudinal direction of the channel (Distance) and impurity concentration (Conc.) in the case of a gate length being 2.03 &mgr;m, 0.52 &mgr;m, and 0.21 &mgr;m, respectively. In the figure, a region of low impurity concentrations corresponds to the channel, and in regions on the opposite sides of the region, corresponding to the source and the drain, respectively, a rise in impurity concentration due to impurity pileup is observed.
A pileup amount reaches the maximum value at the edges of the gate, close to the position where the S/D ion implantation has been carried out, and decreases towards the channel. It is regarded that the reverse short channel effect of a MOSFET, whereby the threshold voltage becomes higher according as the gate length becomes shorter, occurs mainly due to the impurity pileup.
FIG. 16
shows relationships between the gate length Lg and the threshold voltage Vth in the case of the substrate bias VB at 0V, −3V, and −5V, respectively.
With a semiconductor device, as dimensions of the device are reduced in an attempt to enhance response speed and a degree of integration, the gate length generally becomes shorter correspondingly. Meanwhile, it is desirable from the viewpoint of circuit designing that the threshold voltage Vth remains constant regardless of the gate length Lg, however, as the gate length Lg becomes shorter (not longer than 1 &mgr;m in FIG.
16
), the reverse short channel effect whereby the threshold voltage Vth undergoes variation, up and down, is observed.
In the conventional modeling of the reverse short channel effect of the threshold voltage of a MOSFET, the following methods have been adopted:
(1) a method of finding electrical characteristics by calculating impurity distribution by use of the Fair model, and by using a fixed electric charge or other factors (for example, an oxide film at the edges of the gate, with thickness Tox, rendered thicker) in place of the impurities piled up; or
(2) a method of finding electrical characteristics directly by calculating impurity distribution by use of the pair diffusion model.
However, with the conventional methods (1) and (2) as described above, several problems have been encountered as follows:
1. with the Fair model, it is impossible to simulate the impurity pileup at the Si/SiO
2
interface;
2. with the Fair model, even by use of the fixed electric charge, and so forth, in place of the impurity piled up, the profile of the impurities is not altered. Accordingly, it is impossible to analyze in detail electrical characteristics such as, for example, dependency of the reverse short channel effect on impurity concentration in the substrate of the MOSFET, or dependency of the reverse short channel effect on the substrate bias;
3. with the pair diffusion model, since a longer time is required for calculation as described in the foregoing, it becomes difficult to adopt the pair diffusion model from the viewpoint of attaining high efficiency in simulation in case that there is the need of executing calculation a plurality of times such as sensitivity analysis of process/device/inter-circuit, process optimization, process fluctuation analysis, calibration of the model parameters, and so forth; and
4. with the pair diffusion model, point defects having high diffusion speeds are dealt with. Accordingly, it is required that a computer for use in simulation has a sufficient space for analysis with the result that a memory for calculation, having a large capacity, becomes indispensable.
In order to overcome the problems as described in the foregoing, the invention has been developed, and it is an object of the invention to provide a semiconductor modeling method, capable of simulating the impurity pileup at the Si/SiO
2
interface, and also capable of analyzing electrical characteristics dependent on the impurity concentration (for example, dependency on the substrate bias) under high-speed calculation.
SUMMARY OF THE INVENTION
For solving the problems as described above, in accordance with a first aspect of the invention, there is provided a semiconductor modeling method comprising a first step of storing data on an SiO
2
layer, a second step of storing data on an Si layer formed so as to be in contact with the SiO
2
layer, a third step of dividing the Si layer into a plurality of regions, and setting an amount of impurity contained in the respective regions, a fourth step of setting an inter-regional migration amount of the impurity contained in the respective regions for a unit of time, a fifth step of constituting an impurity pileup part in the vicinity of an interface between the SiO
2
layer and the Si layer, and a sixth step of calculating impurity distributi
Niebling John F.
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
Whitmore Stacy A
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