Dual bank flash memory device and method

Details Dual bank flash memory device and method Dual bank flash memory device and method

2001-08-02

2003-04-22

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230030, C365S230020

Reexamination Certificate

active

06552935

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a nonvolatile memory device, and particularly to a user-configurable, dual bank flash memory device.
2. Description of the Related Art
The first nonvolatile memories were electrically programmable read-only memories (EPROMs). In these memories, the memory cells include a floating-gate transistor that is programmable using the hot carrier effect. Programming of an EPROM memory cell includes applying a potential difference between the drain and the source of the floating gate transistor in the presence of a high potential difference (of about 20 volts, this value varying according to the desired programming speed) between the control gate and the source. The application of the first of these potential differences generates an electrical field that gives rise to a flow of electrons in the channel. These electrons collide with atoms of the channel, causing the appearance of new free electrons. These electrons have very high energy (hence the term “hot carriers”). The high difference in potential between the control gate and the source of the floating gate transistor gives rise to a strong electrical field between the floating gate and the substrate, the effect of which is that certain of these electrons are injected into the floating gate, thus putting the memory cell in a state known as a “programmed” state.
The fact that the programming of a memory cell requires the application of voltages both to the control gate and to the drain of the floating-gate transistor eliminates the need for the use of a selection transistor to program one particular memory cell without programming the others. This results in a relatively small silicon area and the effectuation of large scale integration. By contrast, the erasure of all the memory cells of the memory is done substantially simultaneously by exposing the memory cells to ultraviolet radiation.
In addressing the need to individually erase EPROM memory cells, electrically erasable programmable read only memories (EEPROMs) were created. These memories are electrically programmable and erasable by tunnel effect (i.e., the Fowler Nordheim effect). The memory cells have a floating-gate transistor whose drain is connected to the bit line by a selection transistor. The gate of the selection transistor is connected to the word line. The gate of the floating-gate transistor is controlled by a bias transistor. Generally, the source of the floating gate transistor is connected to a reference potential, such as ground. These floating-gate transistors have an oxide layer between the substrate and the floating gate that is very thin to enable the transfer of charges by tunnel effect. The advantage of EEPROMs as compared with EPROMs lies in the fact that each memory cell is programmable and erasable independently of the other EEPROM cells. The tradeoff here is that a larger surface area of silicon is required and therefore a smaller scale of integration is achieved.
A third type of memory has more recently gained popularity. This type of memory, flash EPROMs, combines the relatively high integration of EPROMs with the ease of programming and erasure of EEPROMs. Flash memory cells can be individually programmed utilizing the hot carrier effect in the same way as EPROM cells are programmed. Flash memory cells are also electrically erasable by the tunnel effect. The memory cells of a flash EPROM memory includes a floating-gate transistor that has an oxide layer whose thickness is greater than the oxide layer thickness of an EEPROM floating gate transistor but smaller than the oxide layer thickness of an EPROM floating gate transistor. Consequently, the flash memory cell is capable of erasure by the tunnel effect. For erasure, a highly negative potential difference is created between the control gate and the source of the floating gate transistor, the drain being left in the high impedance state or connected to the ground potential so that a high electrical field is created which tends to remove the electrons from the floating gate.
Flash EPROM devices, hereinafter referred to as flash memory devices, typically include at least one array of flash memory cells organized into rows and columns of flash memory cells. The array is typically partitioned into blocks, each of which is further divided into sectors. A row decoder and column decoder are used to select a single row and at least one column of memory cells based upon the value of an externally generated address applied to the flash memory device. Sense amplifiers are coupled to the column lines corresponding to the columns of memory cells to amplify the voltage levels on the addressed column lines corresponding to the data values stored in the addressed flash memory cells. The particular implementations of the array and the row and column decoders are known in the art and will not be described further for reasons of simplicity.
Because memory modify operations (memory program or memory erase operations) typically take a good deal of time to execute, relative to memory read operations, flash memory devices have been implemented as dual bank memory devices in order to be able to perform memory read operations while a memory modify operation is being performed. In a conventional dual bank flash memory, the array of memory cells is partitioned into two independently accessible banks. The partitioning of the array into the two banks is performed during device fabrication and particularly at metalization. In other words, the metal masks determine the partitioning of the array.
A known dual bank flash memory is illustrated in FIG.
1
. In this flash memory device, the array A of memory cells is capable of being partitioned to provide a 1/8-7/8, 1/4-3/4 or 1/2-1/2 dual bank ratio. Sense amplifiers SA are likewise partitioned to correspond to the partitioning of the array A. Each bank is associated with a distinct row decode circuitry RD and column decode and/or predecode circuitry CD. The decode circuitry of each bank is capable of receiving a predecoded address corresponding to a memory read operation or a memory modify operation (i.e., a memory read or a memory erase operation). The address for the memory read operation is provided by read address circuitry RAC, such as an address register, that is coupled to the address input of the memory device. The address for the memory modify operation is provided to each decoder circuit by an address counter AC having an input coupled to the address input of the memory device. A control circuit CC controls the various circuits of the flash memory device so as to execute memory read and memory modify operations.
Because array A is partitioned during device fabrication by using any of a plurality of metal mask sets, one shortcoming of prior dual bank flash memory devices is that the user is unable to partition array A as desired in the field. In addition, the costs of fabrication are heightened due to the multiple sets of metal masks having to be available for use during fabrication. Based upon the foregoing, there is a need for a dual bank flash memory device that allows greater flexibility in partitioning at reduced costs.
SUMMARY OF THE INVENTION
Embodiments of the present invention overcome shortcomings in prior nonvolatile memory devices and satisfy a significant need for a nonvolatile memory device having multiple core banks that are relatively easily and inexpensively configured into two banks so as to form a dual bank memory device. The two dual banks may be configured to have different sizes. The core banks are user configurable using programmable logic, thereby eliminating the need for multiple sets of metal masks to define bank configuration.
The nonvolatile memory device includes more than two core banks of nonvolatile memory cells. Memory cells in each core bank are arranged in addressable rows and columns of nonvolatile memory cells. The memory device further includes a plurality of address decode circuits, each address decode circuit being associated with a dis

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