Coded data generation or conversion – Digital code to digital code converters
Reexamination Certificate
2001-08-01
2003-04-01
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
C341S082000, C327S407000, C327S408000, C326S119000, C326S121000
Reexamination Certificate
active
06542093
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention generally relates to data transmission, and more particularly, to reducing noise production and power consumption using reduced switching recoding in monotonic logic device.
2. Description of Related Art
Currently, many arithmetic operations in present processor implementations are accelerated by utilizing a floating-point processor. These floating-point processors can include multipliers using radix multiplication and carry save adders to increase the performance of multiplication operations.
Generally, there are two popular stages of radix multiplication for carry save adders. High radix multiplication (radix 8 or greater) and low radix multiplication (radix 4 or lesser). High radix multiplication has the advantage of requiring fewer partial products to be generated and summed, however, high radix multiplication also requires that complex multiples of the X operand to be generated. Low radix multiplication (radix 4) is therefor a preferable implementation for executing multiplication due to the simple multiples of the X operand to be generated.
Illustrated in to
FIG. 1A
, is the radix 4 booth recoding multiplication table 2, the 3 multiplier bits and X operand multiples. As can be seen for radix 4 booth recoding multiplication, only the simple multiples of zero, 1X and 2X are required for the operand. As it is known in the art, a multiple of a number can be easily generated for the zero, one and two multiples. A zero multiple requires only that the value be reset, zeroed out or cleared out. A negative one multiple requires that the complement of the operand be obtained. A multiple of two for a number is easily generated for the number by performing a left shift by one position on the number. A negative multiple of two times a number is obtained by acquiring the complement of the multiple of two number.
Illustrated in
FIG. 1B
is a table 3 illustrating the traditional domino encoding method for operand multiples, that is normally implemented in radix 4 circuitry. As can be seen, traditional domino encoding requires that 2 of 5 wires be enabled to indicate the proper operand multiples: 0, ±1X or ±2X radix 4 output, as shown in the radix 4 multiplication table 2 (FIG.
1
A). For power and noise reasons, it is desirable to reduce the number of wires routed over the carry save adder array and the switching activity of these wires.
Illustrated in
FIG. 1C
is a block diagram of a possible example of a multiplexer circuit
14
that utilizes a traditional domino encoding technique illustrated in
FIG. 1B
to output a final product. The circuit
11
is comprised of 0 times the multiplier
12
, 1 times the multiplier
13
, and 2 times the multiplier
14
signals. All these signals (
12
-
14
) are utilized as input into the 3:1 MUX
15
. The 3:1 MUX
15
accepts the three multipliers
12
,
13
and
14
signals as input and has signal lines
16
(A-C) to select the appropriate output.
Upon using the proper selection lines
6
(A-C), the proper input signal
12
,
13
, or
14
is output of the 3:1 MUX
15
and input into the exclusive or “XOR”
18
. The “XOR”
18
accepts the correct multiplier signal from the 3:1 MUX
15
, and a sign signal
17
to output the appropriate output on line
19
. A schematic of the radix 4 booth encoded multiplexer
15
is herein defined in further detail with regard to FIG.
1
D.
Illustrated in
FIG. 1D
is a schematic of the radix 4 booth encoded multiplexer
15
with 2 of 5 encoding, as shown in FIG.
1
C. As shown in
FIG. 1D
, the radix 4 booth multiplexer with 2 of 5 encoding of the prior art, requires 22 transistors for the circuit in 4 series of N-fets to generate the output. This 4 high N-fet stack can be slow and does require significant loading on the lines to preserve the correct values.
Illustrated in
FIG. 1E
is a table 21 illustrating a carry save adder array multiplier operation. Emphasized are the partial products generated during the multiplication operation. Portions of the partial products generated are considered non-critical drop-off bits
26
. A non-critical partial product drop-off bit
26
, is best described as a bit that is determined (i.e. fixed) very early in the cycle time of the overall logic device operation. Since this non-critical partial product drop-off bit
26
is determined very early in the cycle time of the overall device operation, it quite often must be carried a great distance and for a long period of time to be utilized in the final product.
For example, in a carry save adder array multiplier for large multiplicands and multipliers (i.e. 64 bit and larger), a great number of non-critical partial product bits can be produced. These large number of non-critical of partial product bits can cause wire routing problems during designed. Also, a large number of non-critical of partial product bits
26
can cause data errors due to the switching activity of the large number of wires. As discussed above, the non-critical partial product bits
26
can cause problems for circuit designers. Therefore, it is desirable to reduce the number of wires routed and the switching activity of these non-critical partial product drop off bits wires over the carry save adder array multiplier and other monotonic logic devices.
Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and method for reducing noise production and power consumption through reduced switching recoding of signals in monotonic logic devices.
Briefly described, in architecture, the apparatus can be implemented as follows. The apparatus includes a recode circuitry that receives and recodes a monotonic logic device signal received from a first logic circuit in a logic device, into a reduced switching activity signal. The recode circuitry sends the reduced switching activity signal to a second logic circuit. A decode circuitry receives and decodes the reduced switching activity signal back into a monotonic logic device signal. The decode circuitry then sends the monotonic logic device signal to a second logic circuit in the logic device.
The present invention can also be viewed as providing method for reducing noise production and power consumption through reduced switching recoding of signals in monotonic logic devices.
In this regard, the method can be broadly summarized by the following steps: (1) receiving a monotonic logic device signal from a first logic circuit; (2) converting the monotonic logic device signal into a reduced switching activity signal; (3) transmitting the reduced switching activity signal; (4) receiving said reduced switching activity signal; and (5) converting the reduced switching activity signal back into a monotonic logic device signal.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.
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Hewlett--Packard Company
Nguyen Linh V
Tokar Michael
LandOfFree
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