Semiconductor memory system

Details Semiconductor memory system Semiconductor memory system

2002-05-30

2003-07-15

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250, C365S189011, C365S204000, C365S207000, C365S051000

Reexamination Certificate

active

06594180

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory system, and more particularly to a non-volatile memory.
BACKGROUND OF THE INVENTION
Conventionally, a type of memory-cell matrix which has a so-called “NOR” or “double-T” structure is used for non-volatile semiconductor memories. In a matrix of this type, the rows or word lines of the matrix which, typically, include polysilicon strips that form the control gates of the cells belonging to these rows, extend parallel to one another in a first direction. Doped regions, for example, n-type doped regions, are formed between alternate pairs of rows and extend parallel to the rows, throughout the length of the rows; each of the diffused regions forms a common source line for the memory cells that belong to the pair of rows between which the doped region is formed. The drains of the cells are formed of n-type doped regions aligned parallel to the rows and formed between alternate pairs of rows, other than those between which the source lines are formed. The columns or bit lines of the matrix include metal lines, typically made of aluminium, which extend parallel to one another in a direction perpendicular to the rows, and which contact the drains.
To select a generic memory cell, the row to which the cell belongs is selected by bringing it to a preselected potential and the column to which the cell belongs is connected electrically to a reading circuit. Typically, the reading circuit performs a reading of the cell via a current. In memories which adopt the above-mentioned type of cell matrix, reading of the memory cells with a current is easy to implement and, for this reason, is widely adopted. The generic memory cell selected is in fact safely insulated from the memory cells adjacent thereto.
Contactless memory structures, which have alternative architectural characteristics to those described above, are also known and enable the overall area occupied by a memory matrix to be reduced. In a contactless memory matrix, n-type doped regions are provided and extend, parallel to one another, in the direction perpendicular to the rows. These regions represent the bit lines of the memory matrix and act alternately as drain and source electrodes for the memory cells to which they are connected.
In these memory matrices, the memory cells include and are delimited by diffusions which extend from the source regions to the drain regions, parallel to the rows, and which partially coincide with the bit lines. The gate terminal of each memory cell is formed by the portion of polysilicon connecting each source diffusion to that of the drain, and can be formed by floating-gate technology, which uses a double polysilicon layer, or by an NROM (nitride read-only memory) technology, using a layer of nitride, or even simply of oxide, that is, with standard MOS technology.
In a contactless matrix, the memory cells are clearly separated by the interposition of suitable insulation regions, but appear contiguous with one another. Moreover, for particular memory cells, contactless matrixes can use a virtual-ground type of architecture. This means that a particular bit line does not have a univocal role but may operate as a source electrode during a first reading or writing operation, whereas it may operate as a drain electrode during a further reading or writing operation.
The ability to use the same bit line as a source or drain electrode, for example, enables reading operations to be performed on memory cells disposed on both sides of the same bit line. Virtual-ground architecture is particularly suitable for memory cells such as, for example, NROM cells, which are read in the opposite direction to that in which they are programmed. In particular, it is known that virtual-ground architecture may advantageously be used for “dual-bit” NROM memory cells which enable one bit to be stored for each side of the cell.
In spite of the advantages offered, contactless and virtual-ground architectures have disadvantages caused by the contiguity of the memory cells and by the need to access a generic cell by non-univocal methods. Up to now, these disadvantages have rendered current reading inapplicable to these structures in practice, unless very low performance of the reading operation is accepted. In fact, the contiguity with which the cells are formed is the cause of a neighbor effect which is manifested by the development of undesired electric currents (leakage currents) between a memory cell which is being read and to which a suitable voltage is applied, and one or more contiguous cells. These leakage currents are not constant but depend on the states (virgin or programmed) of the cells contiguous to those being read.
The presence of leakage currents degrades the current affecting the cell being read, reducing the performance of the operation. Moreover, the fact that the role of each bit line is not univocal in virtual-ground structures complicates the production of circuits which control the methods of access to a cell of the memory matrix. This difficulty is further increased when dual-bit cells are used.
For these reasons, conventional reading with current is replaced, for example, by techniques which use a dynamic approach. The dynamic approach is based on an analysis of the capacitive behaviour of the cell being read and of that of a reference cell. These techniques are particularly complex and expensive and, above all, are not immune to the above-mentioned neighbor effects.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory system in which the above-described leakage-current phenomenon is avoided so that it is possible to implement an advantageous reading of the memory cells with current.
The object of the present invention is achieved by a memory system including a memory matrix formed on a semiconductor structure. The memory matrix includes a first column line and a second column line which are connected electrically to at least one first memory cell to be read. For the reading of the at least one first cell, a first reading voltage can be supplied to the first column line. The memory matrix also includes a third column line distinct from the first column line and from the second column line. The memory matrix further includes generating circuit for supplying, to the third column line and during the reading of the at least one first memory cell, a biasing voltage which can oppose the establishment of an electric current between the first column line and the third column line in the semiconductor structure. The biasing voltage is preferably substantially equal to the first reading voltage.


REFERENCES:
patent: 5448518 (1995-09-01), Jinbo
patent: 6181597 (2001-01-01), Nachumvosky
patent: 0 791 936 (1997-08-01), None
patent: 2 272 089 (1994-05-01), None
Abstract of the 1996 International Conference on Solid State Devices and Materials, Yokohama, 1996, pp. 269-271 entitled “A Novel NOR Virtual-Ground Array Architecture for High Density Flash”; XP 000694045.
Tsao et al.: “A 5V-Only 16M Flash Memory Using A Contactless Array of Source-side Injection Cells”, 1995 Symposium on VLSI Circuits, Kyoto, Jun. 8-10; pp. 77-78. XP000557809.

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