Semiconductor integrated circuit and test board

Details Semiconductor integrated circuit and test board Semiconductor integrated circuit and test board

2001-08-02

2003-04-29

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C714S726000

Reexamination Certificate

active

06556037

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having therein a test controller for carrying out a test for verifying the semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
Finer processing of a semiconductor integrated circuit (hereinbelow, also called an LSI (Large Scale Integrated Circuit)) enables a larger number of devices to be integrated on a chip. Particularly, the circuit scale is being enlarged at a very fast pace, for example, Moore's law predicts that “the number of transistors integrated on an IC will double approximately every 18 months”. Also in a shipment test for screening a defective LSI, the scale of a circuit to be tested is inevitably being enlarged, so the test pattern necessary for the test is becoming more complicated, and the number of test patterns is increasing.
In order to facilitate a test conducted on such an LSI, a method called the JTAG (Joint Test Action Group) test defined by IEEE standard 1149.1 is used. The JTAG test is carried out by sequentially scanning all the external input/output pins of an LSI to input/output test data, thereby checking the internal function of the LSI and a printed circuit board on which the LSI is mounted. Therefore, a test according to the method is carried out on a precondition that an LSI as a circuit on the printed circuit board supports the JTAG testing method.
The JTAG test will be briefly described hereinbelow.
FIG. 10
is a diagram showing a schematic configuration of a test system for explaining the JTAG testing method. The LSI
800
compatible with the JTAG standards has therein not only the core logic
810
having the inherent functions of the LSI, but also a test logic constructed by four registers and a TAP (Test Access Port) controller
830
for controlling the registers. The registers are divided into data registers and instruction registers. The data resisters include boundary scan registers (BSR), bypass registers, and option registers. The instruction register, bypass register, and option register have not been shown FIG.
1
.
The LSI
800
is largely different from other LSIs with respect to the point that a shift register, called a cell
821
, is disposed between the core logic
810
and each of the pins of the LSI. By the cells
821
, an event occurring at each of the pins can be observed. That is, the cell
821
has the same function as a test probe. The BSR
820
is obtained by connecting the cells
821
in series and has the important function in the JTAG test. As the number of pins of the LSI increases, the number of bits of the BSR
820
also increases.
The JTAG test method is conducted in two operational modes of a normal mode and a test mode. In the normal mode, the LSI
800
performs normal operation without recognizing the existence of the BSR
820
. Consequently, data passing through each of the pins of the LSI
800
can be captured at an arbitrary timing without exerting an influence on the operation of the LSI
800
. The captured data is shifted a plurality of times, resultant data is outputted from a terminal TDO, and received and verified by an LSI tester
850
for shipping (hereinbelow, simply called a tester). In such a manner, the LSI
800
under the operating condition can be observed.
On the other hand, in the test mode, the core logic
810
in the LSI
800
is isolated from the pins. Consequently, the core logic
810
of the LSI
800
cannot substantially receive/send data from/to the outside of the LSI, and only data of a test pattern is given from the BSR
820
. In the test mode, first, by using an EWS (Engineering Work Station) or the like, data (hereinbelow, called a test pattern) supplied by the BSR
820
to each of the pins is generated, and the test pattern is supplied to a terminal TDI of the LSI
800
via the tester
850
. The tester
850
supplies a control program which runs on a TAP controller
830
to the terminal TDI as necessary.
The TAP controller
830
supplies the input test pattern to the core logic
810
at a timing according to a predetermined control program and outputs the result from the terminal TDO. In a manner similar to the normal mode, the tester
850
receives the output pattern from the terminal TDO and verifies the LSI
800
.
On the side of the tester, however, there is a limitation in the size of a memory mounted for storing test patterns, of which the number increases as the scale of the LSI is enlarged. When a test for all circuit functions of the LSI is conducted, the test has to be conducted a plurality of times. When the test is conducted a plurality of times, the pre-shipment test time largely increases, the manufacturing throughput of the LSI deteriorates, and the manufacturing cost of the LSI increases.
In practice, as a testing method other than the JTAG testing method, a testing method called a scan test is generally carried out in the field of an ASIC (Application Specific IC) and the like. The scan test is realized by test facilitating designing for preliminarily carrying out wiring dedicated to a test so that test data can be directly written in a register in the LSI. Under the current circumstances, however, also in the scan test, an event such that the memory size of the tester becomes short often occurs.
It is, therefore, very important to conduct a shipment test of the same contents (circuit functions) by using test patterns as little as possible. In the conventional testing method, input patterns and output expectation values are prepared for all the input/output pins. The input values and output expectation values of pins which are unnecessary for a test are also loaded on the tester in spite of the fact that the values become invalid at the time of the test, and the memory is cluttered with the values.
FIG. 11
is a diagram for explaining the problems of the conventional testing method. As shown in
FIG. 11
, the tester
850
loads, for example, test patterns for the pins P
1
to P
6
shown in
FIG. 10
in a full period on the memory of the tester
850
, enters an input pattern, and compares an output pattern with output expectation values every period. The output pin P
3
and the input/output pin P
5
are pins unnecessary for the test. However, patterns which are substantially invalid are prepared also for the pins P
3
and P
5
.
SUMMARY OF THE INVENTION
It is an object of this invention to obtain a semiconductor integrated circuit having therein a test controller for generating test patterns for all of pins from test patterns only for pins which are necessary for a test.
In the semiconductor integrated circuit according to the present invention, the test controller generates test patterns for all the pins from test patterns for only pins necessary for the test. The test controller receives information on pins to be tested and first input test patterns constructed by input values and output expectation values for the pins to be tested. The test controller sets the input values or output expectation values of pins which are not to be tested to predetermined values and thereby generates a second input test pattern in which the input values or output expectation values of all the pins are set. The second input pattern is provided to the core logic. The core logic outputs values to predetermined pins in accordance with the second input test pattern. The test controller discards output values corresponding to each of the pins that are not to be tested from the obtained first output test pattern and thereby generates a second output test pattern in which output values corresponding to each of the pins that are to be tested are set. Finally, the test controller outputs the second output test pattern generated by the output test pattern generation unit to the tester.
The test board according to the present invention can mount a plurality of the semiconductor integrated circuits according to the present invention.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


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