Digital sample rate converters having matched group delay

Details Digital sample rate converters having matched group delay Digital sample rate converters having matched group delay

2001-06-07

2003-03-11

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Data rate conversion

C708S313000

Reexamination Certificate

active

06531970

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to digital sample rate converters and, more particularly, to techniques for insuring matched group delay among two or more digital sample rate converters operating with one or more input clocks having the same or nearly the same frequencies and with one or more output clocks having the same or nearly the same frequencies.
BACKGROUND OF THE INVENTION
Audio recording studios commonly digitize signals produced by analog sources, such as microphones. In these studios, audio recording, production, editing and processing are performed in the digital domain. For this reason, most modem digital audio equipment is equipped to receive digital input signals and to provide digital output signals. There is, however, no established standard for a digital sampling rate. Accordingly, digital sample rate converters have been developed to permit digital interfacing between systems that operate at different sample rates.
Digital sample rate converters receive input samples at the sample rate of an input clock and provide output samples at the sample rate of an output clock. Asynchronous sample rate converters are capable of converting between any two sample rates, and the ratio of these rates may be irrational. A purpose of an asynchronous digital sample rate converter is to decouple the sampling rate of the input and output data streams from the clock frequencies used in the processing or storage of these data streams. In addition, an asynchronous sample rate converter may follow slow variations of the input and output sample rates. An asynchronous digital sample rate converter is described in U.S. Pat. No. 5,475,628, issued Dec. 12, 1995 to Adams et al; U.S. Pat. No. 5,666,299 issued Sep. 9, 1997 to Adams et al; and U.S. Pat. No. 6,141,671 issued Oct. 31, 2000 to Adams et al.
It is frequently desirable to operate two or more digital sample rate converters with one or more input clocks having the same or nearly the same frequencies and with one or more output clocks having the same or nearly the same frequencies. For example, audio applications may require the outputs of several microphones to be connected in parallel to audio recording and/or processing equipment. In such applications, multiple sample rate converters may be utilized. Each sample rate converter receives input data at a sample rate determined by an input clock and converts the input data to a sample rate determined by an output clock. The output clock sample rate can be asynchronous or synchronous with respect to the input clock sample rate.
In order to sample rate convert the input data from the input clock rate to the output clock rate, the sample rate ratio, i.e., the ratio of the input clock rate to the output clock rate, is measured by the sample rate converter. The sample rate ratio is used to adjust the length of an FIR filter that is used to prevent aliasing in the sample rate conversion. Since the sample rate ratio of the clock rates may be an irrational number, each sample rate ratio measurement may vary by one least significant bit from the previous sample rate ratio measurement. If the sample rate ratio is updated each time it is measured, the length of the FIR filter may oscillate by one least significant bit, causing distortion in the output data. To avoid such oscillations, hysteresis is introduced such that the sample rate ratio is updated only if it varies by at least two significant bits.
In a multiple sample rate converter configuration, the hysteresis produces slightly different sample rate ratio measurements in the different sample rate converters. Therefore, the lengths of the FIR filters in the different sample rate converters are slightly different as well. The group delay, which is the delay of the input data through the sample rate converter, is a function of the FIR filter length, which in turn is a function of the sample rate ratio. Thus, when the sample rate ratio varies between multiple sample rate converters, the group delay through the sample rate converters is slightly different as well. When the data being sent through the sample rate converter is linear PCM audio data, the delay differences between sample rate converters result in phase differences in the audio signals. Such phase differences reduce the fidelity of audio processing and may be unacceptable. For example phase differences may shift the location of the sound or may result in cancellation of the sound.
Accordingly, there is a need for methods and apparatus for matching the group delay between two or more digital sample rate converters.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a method is provided for operating two or more sample rate converters. The method comprises the steps of providing an input clock to each of the sample rate converters, providing an output clock to each of the sample rate converters, measuring a sample rate ratio of the clocks in one of the sample rate converters, designated as a master, and controlling each of the sample rate converters with the sample rate ratio measured by the master.
Typically, the sample rate ratio of the input clock to the output clock is measured. Depending on the system configuration, a single input clock or two or more input clocks may be used. Furthermore, a single output clock or two or more output clocks may be used.
Preferably, the measured sample rate ratio is transmitted from the master to each of the other sample rate converters. The sample rate ratio may be transmitted on an output data line of the master. Each of the sample rate converters may select an internal or an external sample rate ratio in response to a mode select input.
According to another aspect of the invention, a sample rate conversion system is provided. The sample rate conversion system comprises a master sample rate converter and one or more slave sample rate converters each adapted for receiving an input clock and an output clock. The master sample rate converter includes a sample rate ratio circuit for measuring a sample rate ratio of the clocks. The one or more slave sample rate converters each includes a sample rate conversion circuit for sample rate conversion according to the sample rate ratio measured by the master sample rate converter.
In one embodiment, the master sample rate converter and the one or more slave sample rate converters have data lines connected in a parallel configuration. In another embodiment, the master sample rate converter and the one or more slave sample rate converters have data lines connected in a daisy chain configuration.
According to a further aspect of the invention, a sample rate converter comprises a sample rate conversion circuit for converting an input signal at a sample rate of an input clock to an output signal at a sample rate of an output clock according to a sample rate ratio, a sample rate ratio circuit for measuring the sample rate ratio of the clock sample rates, and a control circuit. The control circuit supplies the sample rate ratio from the sample rate ratio circuit to the sample rate conversion circuit in a first operating mode and supplies the sample rate ratio from an external source to the sample rate conversion circuit in a second operating mode.


REFERENCES:
patent: 5289116 (1994-02-01), Kurita et al.
patent: 5448193 (1995-09-01), Baumert et al.
patent: 5475628 (1995-12-01), Adams et al.
patent: 5631931 (1997-05-01), Takano et al.
patent: 5666299 (1997-09-01), Adams et al.
patent: 5875354 (1999-02-01), Charlton et al.
patent: 6057789 (2000-05-01), Lin
patent: 6141671 (2000-10-01), Adams et al.
Analog Devices, Inc., AD1896 Specification, 192kHz Stereo Asynchronous Sample Rate Converter, 2001, pp. 1-24.
“An Asynchronous Sample Rate Converter with 120 dB THD+N Supporting Rates up to 192 kHz”, K. McLaughlin et al, AES 109thConvention, Los Angeles, Sep. 22-25, 2000, pp. 1-8.

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