Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With provision for cooling the housing or its contents
Reexamination Certificate
2001-10-31
2003-07-22
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With provision for cooling the housing or its contents
C257S781000, C257S784000, C257S691000
Reexamination Certificate
active
06597065
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of semiconductor devices and processes and more specifically to thermally enhanced configurations of semiconductor chips having bonds over active circuits and to a method of fabricating these configurations using power distributions integrated into the chip surface.
DESCRIPTION OF THE RELATED ART
Removing the thermal heat generated by active components belongs to the most fundamental challenges in integrated circuit technology. Coupled with the ever shrinking component feature sizes and increasing density of device integration is an ever increasing density of power and thermal energy generation. In order, however, to keep the active components at their optimum (low) operating temperatures and speed, this heat must continuously be dissipated and removed to outside heat sinks. This effort, unfortunately, becomes increasingly harder, the higher the energy density becomes.
In known technology, the most effective approach to heat removal focuses on thermal transport through the thickness of the semiconductor chip from the active surface to the passive surface. The passive surface, in turn, is attached to the chip mount pad of a metallic leadframe so that the thermal energy can flow into the chip mount pad of the metallic leadframe. When properly formed, this leadframe can act as a heat spreader to an outside heat sink. In many semiconductor package designs, this implies a leadframe with a portion formed such that this portion protrudes from the plastic device encapsulation; it can thus be directly attached to the outside heat sink. Examples are described in U.S. Pat. No. 5,594,234, issued on Jan. 14, 1997 (Carter et al., “Downset Exposed Die Mount Pad Leadframe and Package”) and U.S. Pat. No. 6,072,230, issued on Jun. 6, 2000 (Carter et al., “Bending and Forming Method of Fabricating Exposed Leadframes for Semiconductor Devices”).
From a standpoint of thermal efficiency, however, these approaches have several shortcomings. First of all, the heat generated by active components must traverse the macroscopic thickness of the semiconductor chip in order to exit from the chip. The heat then faces the thermal barrier of the attach material (typically a polymer) before it can enter the leadframe. Secondly, a technical solution is missing to remove the heat generated by active components directly from the IC into a metallic heat conductor and heat spreader positioned in microscopic proximity to the active component. The usual approach is to first spread the heat through the macroscopic thickness of the molding material (typically an epoxy filled with inorganic particles, a mediocre thermal conductor) and only then into a metallic heat spreader, usually positioned on the surface of the molded package.
The thermal situation is also difficult in a conventional ball-grid (or land-grid) array package. A BGA package generally includes an IC chip, a multi-layer substrate, and a heat spreader. The chip is generally mounted on the heat spreader using a thermally conductive adhesive, such as an epoxy. The heat spreader provides a low resistance thermal path to dissipate thermal energy, and is thus essential for acceptable thermal performance during device operation, necessary for consistent electrical performance. Further, the heat spreader provides structural and mechanical support by acting as a stiffener, adding rigidity to the BGA package, and may thus be referred to as a heat spreader/stiffener.
In contrast to the advantages of the BGA packages, prevailing solutions in BGA packages have lagged in performance characteristics such as power dissipation and the ability to maintain signal integrity in high speed operation necessary for devices such as high speed digital signal processors (DSP) and mixed signal products (MSP). Electrical performance requirements are driving the need to use multi-layer copper-laminated resin substrates (previously ceramic). For higher speeds, flip chip assembly rather than wire bonding has been introduced. Compared to wire bonding within the same package outline, flip chip assembly offers greatly reduced IR drop to the silicon core circuits; significant reduction of power and ground inductances; moderate improvement of signal inductance; moderate difference in peak noise; and moderate reduction in pulse width degradation. An example for some electrical improvements of BGA packages is described in U.S. patent application Ser. No. 09/645,760, filed Aug. 25, 2000 (James et al., “Ball Grid Array Package having Two Ground Levels”).
Until now, however, substantial thermal improvements of BGA packages, both of flip-chip and wire bonded chip assemblies, have been lacking. This is especially true for any low-cost thermal advancement, since any cost-adding technical proposal is contrary to the strong market emphasis on total semiconductor device package cost reduction.
An urgent need has therefore arisen to break this vicious cycle and conceive a concept for a low-cost, thermally improved and electrically high performance BGA package structure. In addition, a general semiconductor package structure is needed which based on fundamental physics and design concepts flexible enough to be applied for different semiconductor product families and a wide spectrum of design and assembly variations. It should not only meet high thermal and electrical performance requirements, but should also achieve improvements towards the goals of enhanced process yields and device reliability. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
In FOURIER's approach to solving the differential equation of thermal conductance, the thermal flux Q per unit of time is equal to the product of thermal conductivity &lgr; multiplied by the gradient of temperature T, in the direction of decreasing temperature, and by the area q perpendicular to the-temperature gradient:
dQ/dt=−&lgr;·
(grad
T
)·
q,
where Q is the vector (in magnitude and direction) of thermal flux, and &lgr; is the thermal conductivity, a materials characteristic. The thermal flux is in the direction of the temperature difference and is proportional to the magnitude of that difference.
When, over the length l, the temperature drop is steady and uniform from the high temperature T
2
to the low temperature T
1
, then (grad T) reduces to (T
2
−T
1
)/l:
dQ/dt=−&lgr;·
(
q/l
)·(
T
2
−
T
1
).
&lgr;·(q/l) is called the thermal conductance, and the inverse value l/(&lgr;·q) is called thermal resistance (in analogy to OHM's law).
In the present invention, improvements of both &lgr;·q and (grad T) are simultaneously provided to enhance the thermal flux vertically away from the heat-generating active components on the active surface of the semiconductor chip.
In addition to this enhanced thermal flux vertically away from the active chip surface, there is the traditional possibility of conducting thermal energy in the opposite direction through the semiconductor material of the chip to its passive surface and beyond into leadframes or other substrates.
The present invention thus provides for optimized thermal performance of integrated circuits, solving one of the most intractable limitations of semiconductor technology.
An integrated circuit (IC) chip has a metal network of electrical power distribution lines which have a thermal conductance at least an order of magnitude greater than underlying thin film electrical interconnects. These lines are deposited on the surface of the chip, located directly over active IC components, and electrically and thermally connected vertically to selected active components below the lines. Electrical conductors are operable to connect the lines to an outside source, and additional electrically non-functional conductors are distributed on the lines, operable to steepen the thermal gradient for thermal flux away from said active components and lines.
The patterned network of
Brady III Wade James
Clark Jasmine J B
Skrehot Michael K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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