Static information storage and retrieval – Powering
Reexamination Certificate
2002-02-26
2003-07-29
Le, Thong Quoc (Department: 2818)
Static information storage and retrieval
Powering
C365S189090, C365S189110
Reexamination Certificate
active
06600692
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2001-052588, filed on Feb. 27, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a semiconductor device having a voltage regulator for output of a regulated voltage that is variable in response to an output voltage of an internal voltage generation circuit.
2. Description of the Related Art
Prior known electrically rewritable non-volatile semiconductor memory devices include electrically erasable programmable read-only memory (EEPROM) chips, also known as “Flash” memories in the semiconductor device art. Currently available Flash EEPROM chips come with an array of rows and columns of nonvolatile memory cells, each of which is typically formed of a metal insulator semiconductor field effect transistor (MISFET) of the so-called “stack gate” structure with a floating gate and a control gate being stacked above a semiconductor chip substrate. Each stack-gate MISFET memory cell stores therein a digital binary data bit of a logic “0” or “1” in accordance with the charge accumulation state of its floating gate. One example is that a storage data bit is assumed to be a logic “0” in the event that the floating gate storing thereon electrons is high in threshold voltage while letting the bit be a logic “1” when the floating gate releases the electrons and thus is low in threshold voltage.
Flash memories include EEPROMs of the NOR type. In the case of such NOR-EEPROMs, a memory cell array is arranged so that a respective one of rows of memory cells is associated with a corresponding one of parallel bit lines in a manner such that drains of these cells are connected together or “common-coupled” to the bit line whereas each column of memory cells is common-coupled at control gates to a corresponding one of parallel word lines that cross over the bitlines. A data write operation is performed after having erased all the cells of the memory array at a time, known as “all-at-a-time” or “all-at-once” erase among those skilled in the art. The all-at-once erase is achievable in a way as follows. Firstly all the wordlines of the memory cell array are applied a voltage of the negative polarity having a specific potential level—typically, −7 volts (V), or more or less. Then, apply a positive voltage of about +10V to a common source, causing electrons presently residing on floating gates to release toward the substrate side by Fowler-Nordheim (F-N) tunneling effects. Whereby, all the memory cells are thus set in the erase state of data “1.”
Data writing on a per-cell basis is done by applying a write voltage of about 10V to a word line being presently selected from among the wordlines and then giving to the selected bitline either one of an on-chip power supply voltage Vdd and a source or “ground” voltage Vss in a way depending on whether the data being written is a logic “0” or “1.” This voltage application results in that in a cell to which logic “0” data is given, “hot” electrons are injected into the floating gate thereof causing its threshold voltage to shift or “offset” in a positive direction. In the case of logic “1” data, no appreciable threshold voltage changes occur.
Data read is done by giving a read voltage to a selected wordline and then detecting the presence or absence of a cell current flow.
In the above operations, the data write is typically combined with a verify-read operation for confirmation or verification of the resulting write state. More specifically, after having written data under application of the write voltage, the verify-read operation is done. Repeated execution of such write voltage application and its following verify-read session forces the threshold voltage of a written memory cell to finally fall within a prespecified distribution range. Similarly in the case of data erase, recurrent execution of erase voltage application and its following erase-verify operation enables the threshold voltage of an erased cell to finally fall within a specified distribution range.
For adequate control of the above-noted operations in the write and erase modes, a need is felt to supply a stabilized and regulated voltage with its potential optimized on a per-mode basis. A presently available approach to generating such a regulated voltage is to employ a voltage regulator with an ability to generate a plurality of types of regulated voltages based on an output voltage of potential rise-up or “booster” circuitry for use as an internal power supply. A scheme using this approach is disclosed, for example, in J. F. Dickson, “On-Chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique,” IEEE Journal of Solid-State Circuits, Vol. SC-11, No. 3, June 1976 at pp. 374-378. Another technique is taught from A. Umezawa et al., “A 5V-Only Operation 0.6 &mgr;m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure,” IEEE J. Solid-State Circuits, Vol. 27, No. 11, November 1992, pp. 1540-1546.
See FIG.
18
. This diagram shows an arrangement of one prior art voltage regulator adaptable for use with Flash EEPROM chips. This regulator shown herein includes a driver unit
1
. The driver
1
has a serial connection of MOS transistors: a PMOS transistor QP
2
for potential pull-up drive, and an NMOS transistor QN
2
for pull-down drive. The pull-up PMOS transistor QP
2
has a source, to which a potentially increased or “boosted” voltage Vpp as output from a potential booster circuit (not shown) is supplied. The pull-down NMOS transistor QN
2
has its source which is coupled to ground. These transistors QP
2
, QN
2
are coupled together at a connection node N
0
, which is for use as an output terminal of a regulated voltage Vreg.
An operational amplifier OP
1
is provided for controlling a gate of the pull-down NMOS transistor QN
2
. It is an ensemble of operational amplifier OP
2
and NMOS transistor QN
1
plus PMOS transistor QP
1
that controls a gate of the pull-up PMOS transistor QP
2
. The NMOS transistor QN
1
is operable under control of an output of the op-amp OP
2
. The PMOS transistor QP
1
functions as a current source load of NMOS transistor QN
1
. PMOS transistors QP
1
, QP
2
make up a current mirror circuit.
The regulator of
FIG. 18
has its output node N
0
, at which a voltage division circuit
2
is provided. This voltage divider circuit
2
includes a serial combination of resistors R
1
to R
3
and a switch element formed of an NMOS transistor QN
3
. Connected to a connection node N
2
of the resistors R
2
-R
3
is an NMOS transistor QN
4
which operates under control of a write-use control signal PROG for coupling the node N
2
to ground. NMOS transistor QN
3
has its gate which is to be controlled by a verify-read control signal VRFY. When NMOS transistor QN
3
is driven to turn on, a connection node N
3
of resistor R
3
and NMOS transistor QN
3
is grounded.
One of the op-amps OP
1
-OP
2
—here, opamp OP
2
—is given a reference voltage Vref at its non-inverting input terminal, with a voltage potential at node N
1
being fed back to an inverting input terminal thereof. The other opamp OP
1
is such that the reference voltage Vref is given to its inverting input terminal while a potential at node N
1
is fed back to its non-inverting input terminal.
This regulator experiences application of feedback control in a way such that the node N
1
of voltage divider
2
becomes equal in potential to the reference voltage Vref being supplied to the opamps OP
1
-
2
whereby it outputs a potentially regulated voltage Vreg with potential “trackability” to a change in boosted output voltage Vpp. More specifically, while the potentially divided output voltage that is obtainable at the node N
1
of voltage divider
2
stays lower than the reference voltage Vref, the opamp OP
1
derives its output voltage of high level causing NMOS transistor QN
1
to turn on whereas an output
Kabushiki Kaisha Toshiba
Le Thong Quoc
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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