Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2001-05-23
2003-07-15
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S565000
Reexamination Certificate
active
06593792
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology for adjusting a delay time of a signal including a clock signal in a semiconductor integrated circuit, and more specifically to the construction of a buffer circuit block and a design method of a semiconductor integrated circuit using the buffer circuit block.
With an increased scale and an increased speed of a semiconductor integrated circuit (called an “LSI” hereinafter), a control of a signal delay time in the inside of the LSI, particularly, a decrease of a clock skew in the LSI including a plurality of circuit blocks operating in synchronism with one clock signal, is strongly demanded more and more. In the prior art, various methods have been proposed for decreasing the clock skew.
Referring to
FIGS. 1A and 1B
,
FIGS. 2A and 2B
, and
FIG. 3
, different prior art methods for decreasing the clock skew are illustrated.
FIG. 1A
is a flow chart for illustrating the process disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-10-011494 (called a “first prior art” hereinafter), and
FIG. 1B
is a circuit diagram showing the example shown in Japanese Patent Application Pre-examination Publication No. JP-A-10-011494. In
FIG. 1B
, the reference number
922
indicates a clock generating circuit, and the reference numbers
923
,
924
,
925
,
926
,
927
,
928
and
929
designate a buffer. The reference numbers
930
,
931
,
932
and
933
show a flipflop. In
FIG. 1B
, only a clock line is shown, so that a signal line is not shown. In a process shown in the flow chart of
FIG. 1A
, in the first prior art, buffers on a clock line in a clock tree are replaced with buffers having a different input logic threshold, so that the delay amount of the buffer is changed by utilizing an output waveform dulling of a preceding stage, whereby the clock skew is decreased.
FIGS. 2A and 2B
show circuit diagrams illustrating clock trees formed in accordance with the method disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-08-274260 (called a “second prior art” hereinafter). In
FIGS. 2A and 2B
, the reference numbers
1011
to
1048
designate drivers having a largest drive capability, and the reference numbers
1022
a
to
1048
a
indicate drivers having a small drive capability. The reference numbers
1051
to
1058
show a flipflop In addition, only a clock line is shown, so that a signal line is not shown. In the circuitry shown in
FIG. 2A
composed of largest drive capability drivers located in accordance with a clock tree method, paths excluding a path having a maximum signal delay value from a second stage in the clock tree to a block circuit (flipflop) are modified by replacing one or more largest drive capability drivers with a previously prepared driver having a small driving capability so that the a signal delay time of each path becomes equal to the maximum signal delay value, whereby a clock skew is decreased.
FIG. 3
is a flow chart illustrating a method disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-10-335470 (called a “third prior art” hereinafter). In this third prior art, a placement and routing are carried out for cells in a sequential circuit operating in synchronism with a clock signal, cells in a combinational circuit operating to receive an output of the sequential circuit, and clock buffer cells for supplying the clock signal to the sequential circuit (Step S
1
). A driving load of the clock buffers in a clock supplying system obtained in the placement and routing is analyzed (Step S
2
), and a driving capability of the clock drivers are set in accordance with the driving load of the clock buffers (Steps S
3
and S
4
), whereby the skew of the clock signal is highly precisely controlled.
The above mentioned methods of the prior art can be said that a buffer in the clock tree is replaced with another, the input logic threshold or the driving capability of the buffer is changed for adjustment of the delay. Accordingly, if it is sufficient if the clock skew is decreased to a certain limited degree, a deserved advantage can be obtained. However, the replacement of the buffer gives influence the characteristics of the clock tree and a peripheral circuit thereof, or alternatively, an input capacitance of the buffer itself changes. Therefore, unless a delay simulation of an actual routing is executed after the buffer replacement, it is not possible to know to what extent the skew is finally decreased. Accordingly, there is a limit in decreasing the skew.
Furthermore, in a specific signal path having a designated highly precise signal delay amount, when the signal delay of the specific signal path exceeds an admissible limit, it becomes necessary to change the placement and routing in blocks on the path.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a buffer circuit block capable of easily and highly precisely controlling the delay of a clock signal or a transmitted signal in a clock supplying system or a signal transmission system of the LSI.
Still another object of the present invention is to provide an LSI design method utilizing the buffer circuit block in accordance with the present invention.
The above and other objects of the present invention are achieved in accordance with the present invention by a buffer circuit block for use in a semiconductor integrated circuit, including an input part, an delay adjusting part and an output part, a delay amount of the delay adjusting part being able to be changed within a predetermined range while fixing at least an input terminal capacitance of the input part having an input terminal and a driving capability of the output part including a load dependency.
According to another aspect of the present invention, there is provided a buffer circuit block for use in a semiconductor integrated circuit, including an input part, an delay adjusting part and an output part, each including a plurality of transistors, a delay amount of the delay adjusting part being able to be changed within a predetermined range while fixing at least the position of an input terminal provided in the input part, the position of an output terminal provided in the output part, an external shape and an external size of the buffer circuit block, the shape and the size of the transistors included in the input part, and the shape and the size of the transistors included in the output part.
In the above mentioned buffer circuit block, the delay amount of the delay adjusting part can be changed within the predetermined range while fixing a placement and routing inhibition region where placement and routing of an element that is not included in the buffer circuit block is inhibited within an area of the buffer circuit block.
Furthermore, the plurality of transistors included in the delay adjusting part can include a plurality of transistors having the same conductivity type but having different sizes.
In addition, the input part can include at least one unitary cell constituted of a p-channel field effect transistor and an n-channel field effect transistor, and the delay adjusting part can include a plurality of unitary cells each constituted of a p-channel field effect transistor and an n-channel field effect transistor.
Furthermore, the output part can include a plurality of parallel-connected unitary cells each constituted of a p-channel field effect transistor and an n-channel field effect transistor.
According to still another aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit which includes at least a clock signal driving circuit block, and a plurality of first circuit blocks operating in synchronism with a clock signal supplied from the clock signal driving circuit block, the method including:
a library preparation step to previously prepare at least one delay adjusting block group including a plur
Choate Hall & Stewart
NEC Electronics Corporation
Nu Ton My-Trang
LandOfFree
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