Semiconductor memory device with improved reference section

Details Semiconductor memory device with improved reference section Semiconductor memory device with improved reference section

2000-08-21

2003-01-14

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S208000, C257S211000, C438S129000

Reexamination Certificate

active

06507052

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly to the improvement of a reference section which generates a reference current for use in identification of data in a memory cell selected.
2. Description of the Related Art
In some methods for reading data from a semiconductor memory device, an electric current ISA flowing through a memory cell and a reference current IRA are compared with each other to make
0
/
1
identification of data. These methods are widely used, for example, in read only memories and the like having flat type memory cells.
For easy understanding of the subsequent description, an explanation will here be made on the general configuration of a typical read only semiconductor memory chip using flat type memory cells to which the present invention is applicable.
FIG. 1
is a plan view showing the general configuration of a semiconductor memory chip using flat type memory cells.
FIGS. 2A and 2B
are plan views showing the general configuration of a unit memory cell block constituting a memory cell array section in the semiconductor memory device and an example of the arrangement thereof, respectively.
FIG. 3
is a plan view schematically showing the positional relation between a metal wiring, serving as a bit line or a virtual ground line, and diffusion regions for contact in a memory cell array section.
Moreover,
FIG. 4
is a schematic plan view showing the arrangement of the contact diffusion regions in each reference cell block constituting a conventional reference section of the semiconductor memory device, in a simplified form for the sake of clarity.
FIG. 5
is a schematic plan view showing an example of the general configuration of this reference section, along with a part of a memory cell array section.
First, referring to
FIGS. 1-3
, a memory chip
1
of the semiconductor memory device using flat type memory cells comprises memory cell array sections
2
, reference sections
3
, decoder sections
4
, peripheral circuit sections
5
, and the like.
To improve the degree of integration, the memory cell array sections
2
are usually composed of memory cell blocks
10
arranged as shown in FIG.
2
B. In the vertical direction, the memory cell blocks
10
are arranged to be symmetric to one another about the border lines thereof, and more specifically, so that they make vertical turns at the respective centers of first contact diffusion regions
13
and second contact diffusion regions
14
in FIG.
2
A. In the horizontal direction, the memory cell blocks
10
are arranged parallel to one another.
Each of the memory cell blocks
10
includes a memory cell part
11
, block selector parts
12
and
19
, and the first and second contact diffusion regions
13
and
14
for establishing connection with a bit line
17
and a virtual ground line
18
. Besides, the memory cell part
11
and the block selector parts
12
,
19
include a plurality of diffusion layers
20
, word lines
21
a,
and block selecting signal lines
22
a.
The diffusion layers
20
are arranged parallel to one another. The word lines
21
a
and the block selecting signal lines
22
a
are orthogonal to the diffusion layers
20
.
As mentioned above, the memory cell array sections
2
comprise the memory cell blocks
10
which are arranged to make turns at the respective centers of the first contact diffusion regions
13
(
13
a
-
13
d,
in
FIG. 3
) and the second contact diffusion regions
14
(
14
a
-
14
d,
in FIG.
3
). With respect to each bit line
17
,
17
a
and each virtual ground line
18
,
18
a,
the first contact diffusion regions
13
,
13
a
-
13
d
and the second contact diffusion regions
14
,
14
a
-
14
d,
along with the contact holes
15
,
15
a
-
15
d
and the contact holes
16
,
16
a
-
16
d,
are arranged in the proportions of ones to two memory cell blocks
10
, thereby establishing connection with the bit line
17
,
17
a
and the virtual ground line
18
,
18
a,
respectively.
Now, referring to
FIGS. 4 and 5
, a conventional reference section
30
in this semiconductor memory device comprises reference cell blocks
31
having the same configuration as that of the memory cell blocks
10
. The reference cell blocks
31
are also arranged to make vertical turns at the respective centers of first contact diffusion regions
32
a
-
32
d
and second contact diffusion regions
33
a
-
33
d.
The contact diffusion regions at required positions, e.g. the first contact diffusion region
32
b
and the second contact diffusion region
33
d
in
FIG. 4
, are provided with contact holes
34
and
35
to establish connection with a bit line
27
and a virtual ground line
28
, respectively.
FIG. 6
is a schematic circuit diagram for explaining the methods of selecting and reading a memory cell in the reference cell when reading data from a memory cell in the semiconductor memory device described above.
Referring to
FIG. 6
, upon data read from a flat type memory cell
611
a,
the value of a current ISA and the value of a current IRA are compared with each other so that their magnitudes are judged by a sense amplifier
600
to make
0
/
1
identification of the data stored in the memory cell
611
a.
Here, ISA is a current that flows through a first contact diffusion region
613
a,
the memory cell
611
a,
and a second contact diffusion region
614
a
to a virtual ground line when a bit line drive circuit
601
gives a potential to the bit line to select the memory cell
611
a.
IRA is a current that flows through a first contact diffusion region
632
a,
a memory cell transistor
671
a,
a second contact diffusion region
633
a,
a memory cell transistor
617
b,
a first contact diffusion region
632
b,
a memory cell transistor
617
c,
and a second contact diffusion region
633
b
to a virtual ground line when a bit line drive circuit
602
gives a potential to the bit line in the reference section.
The memory cell transistors, however, vary in ON current value ISO because of fluctuations in manufacture conditions and the like. Accordingly, IRA is usually set to 1/k of ISO (where k is an integer not smaller than “2”) for surer data identification.
In this example, the three reference cell blocks
631
a
-
631
c
are connected in series to set the reference current value IRA to ⅓ the ON current value ISO of the memory cell transistors.
In recent years, finer processes have increased variations in device characteristics (a drop in ON current, a rise in OFF current (leak current), and the like) even within an identical chip. Accordingly, there has been an increasing need for the finer settings of the reference current value IRA so as to improve the accuracy of the data identification in memory cells.
Nevertheless, the conventional reference section
30
is constituted so that the reference cell blocks
31
having the same configuration as that of the memory cell blocks
10
make turns at the centers of the respective contact diffusion regions as in the memory cell array sections
2
. Therefore, the bit line
27
or the virtual ground line
28
, consisting of metal wiring, and the first and second contact diffusion regions
32
a
-
32
d,
33
a
-
33
d
come into such physical relation as shown in FIG.
4
.
In general, connecting a plurality of reference cell blocks
31
in series requires that a current path also run from a first contact diffusion region
32
a
-
32
d
through the reference cell blocks
31
and reach a virtual ground line
28
via a second contact diffusion region
33
a
-
33
d.
Thus, the positions to connect the bit line
27
and the virtual ground line
28
with the first contact diffusion region
32
a
-
32
d
and the second contact diffusion region
33
a
-
33
d,
respectively, determine the number of blocks in the serial connection.
Since the first contact diffusion regions and the second contact diffusion regions are arranged alternately in the proportions of ones to two reference cell blocks
31
as shown in
FIG. 4
, the reference cell blocks
31
connected in series ca

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