Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2000-09-18
2003-03-25
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
Reexamination Certificate
active
06538588
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic circuits. More particularly, the present invention relates to a novel and improved sigma-delta analog-to-digital converter (&Sgr;&Dgr; ADC).
2. Description of the Related Art
An analog-to-digital converter (ADC) is an important component in many electronic circuits, and is especially important in digital communication systems. An ADC converts a continuous analog waveform into discrete samples at evenly spaced time intervals and also digitizes the amplitude of the signal. The samples can subsequently be processed by other digital signal processing blocks to provide enhancement, compression, and/or error detection/correction of the sampled data. Exemplary applications which require ADCs are code division multiple access (CDMA) communication system and high-definition television (HDTV).
Some important performance parameters of an ADC include linearity, DC offset, and signal-to-noise ratio (SNR). Suboptimal values for these parameters can cause degradation in the performance of a communication system. Linearity relates to the difference between an actual transfer curve (digital output versus analog input) and the ideal transfer curve. For a flash ADC, good linearity is more difficult to obtain as the number of bits in the ADC increases. The DC offset can degrade the acquisition and tracking performance of phase locked loops and the error detection/correction capability of the decoder, such as the Viterbi decoder. SNR can affect the bit-error-rate (BER) performance of the communication system because the quantization and circuit noise from the ADC results in degradation of the sampled data.
In many communication systems, the received RF signal is downconverted to baseband before quantization. Typically, the received signal is downconverted from an RF frequency to an intermediate frequency (IF) in the first downconversion stage. The first downconversion allows the receiver to downconvert signals at various RF frequencies to a fixed IF frequency where signal processing can be performed. For example, the fixed IF frequency allows for a fixed bandpass filter, such as a surface acoustic wave (SAW) filter, to remove undesirable images and spurious responses from the IF signal before the second downconversion stage. The IF signal is then downconverted to baseband where sampling is performed to provide the digitized baseband samples.
In most communication applications, an ADC is required at the receiver. In some applications, the receiver is a commercial unit where cost and reliability are important design criteria because of the number of units produced. Furthermore, in some applications, such as a CDMA mobile communication system, power consumption is critical because of the remote/portable nature of the receiver.
In the prior art, a flash ADC or a successive approximation ADC is used to sample the received signal. In the flash ADC, the input signal is compared against L-
1
reference voltages, which are generated by a resistive ladder, by L-
1
comparators. Flash ADCs are bulky and consume large amount of power because L-
1
comparators and L resistors are required. Furthermore, flash ADCs can have poor linearity and poor DC offset characteristics, if the L resistors in the resistive ladder are not matched. However, flash ADCs are popular because of their high speed.
Successive approximation ADCs are also often used in communication systems. These ADCs minimize complexity by performing approximations of the input signal over two or more stages. However, these ADCs can also exhibit the same poor linearity and poor DC offset characteristics as exhibited by the flash ADCs. Therefore, successive approximation ADCs as well as flash ADCs are not ideal candidates for use in many communication applications.
SUMMARY OF THE INVENTION
The present invention is a novel and improved sigma-delta analog-to-digital converter (&Sgr;&Dgr; ADC). The &Sgr;&Dgr; ADC design allows for high performance, high speed, and low cost. The high performance exhibited by &Sgr;&Dgr; ADCs includes high signal-to-noise ratio (SNR), good linearity, and low DC offset. In a bandpass state &Sgr;&Dgr; modulator, DC offset is typically not an issue. &Sgr;&Dgr; ADCs can be designed using a single-loop architecture or a MASH (Multi-stAge noise SHaping) architecture. &Sgr;&Dgr; ADCs can be implemented as a bandpass or baseband ADC depending on the selection of the filters used within the feed back loops. The filters determine the noise transfer function of the &Sgr;&Dgr; ADC which, in turn, determines the frequency response of the quantization noise. &Sgr;&Dgr; ADCs can be synthesized with numerous analog circuit techniques such as active-RC, gm-C, MOSFET-C, switched capacitor, and switched current. Furthermore, the switched capacitor and switched current circuits can be implemented with single-sampling, double-sampling, quadruple-sampling, or multi-sampling circuits.
An embodiment of the invention provides a sigma-delta analog-to-digital converter that includes at least one loop. Each loop receives a loop input signal and provides a loop output signal. Each loop includes at least one loop section coupled to a quantizer. Each loop section includes N signal paths, with each signal path in a particular loop section being clocked by a set of clock signals having phases unique from those of remaining signal paths in the particular loop section. The quantizer receives and quantizes the signal from the last loop section to provide the loop output signal. In a specific design, the converter includes two loops, with each loop including two loop sections and each loop section being implemented with a resonator.
N can be two, four, or some other integer. For N=4, the first signal path can be clocked by clock signals having first and third phases, the second signal path can be clocked by clock signals having second and fourth phases, the third signal path can be clocked by clock signals having third and first phases, and the fourth signal path can be clocked by clock signals having fourth and second phases.
Each loop section can comprise a lowpass circuit or a resonator circuit. The circuits can be implemented with double-sampling, quadruple-sampling, or multi-sampling switched capacitor circuit technique. Based on, for example, a required dynamic range, one or more loops can be selectively disabled and the bias current of one or more circuits can also be adjusted to conserve power.
Another embodiment of the invention provides a sigma-delta analog-to-digital converter that includes a number of loops, at least one feed-forward gain element, and a noise cancellation logic. The loops couple in cascade and are implemented with N-sampling circuitry. Each loop implements a filter function. The N-sampling circuitry for each loop samples a respective loop input signal at N phases of a clock signal. One feed-forward gain element couples between each pair of sequential loops. The noise cancellation logic couples to the loops. Each loop includes at least one loop section coupled in cascade and a quantizer coupled to the loop section(s). Each loop section can be implemented with a bandpass or lowpass filter.
REFERENCES:
patent: 5982315 (1999-11-01), Bazarjani
An 81-MHZ IF Receiver in CMOS, Hairapetian in IEEE Journal of Solid State Circuits vol. 31, No. 12 Dec. 1996, pp. 1981-1986.*
Schreier, R. Multibit Bandpass Delta-Stigma Modulators Using N-path structures, 1992 IEEE International Symposium on Circuits and Systems, ISCAS '92, vol. 2 pp. 593-596, May 1992.*
Yu, L. et al., A Novel Adaptive Mismatch Cancellation System for Quadrature IF Radio Receivers, IEEE Transactions on Circuits and Systems—II Analog and Digital Signal Processing, vol. 46, No. 6 pp. 789-801, Jun. 1999.*
Bazarjani et al., A 160-MHz Fourth Order Double Sampled SC Bandpass Sigma-Delta Modulator, IEEE Transactions on Circuits and Systems—II Analog and Digital Signal Processing, vol. 45, No. 5 pp. 547-555, May 1998.
Brown Charles D.
Qualcomm Incorporated
Seo Howard H.
Wadsworth Philip R.
Williams Howard L.
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