Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-03-25
2003-09-16
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
Reexamination Certificate
active
06621322
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a level shift circuit, and, more particularly, to a level shift circuit which transfers signals of different supply voltages.
As the versatility of the functions of semiconductor integrated circuit devices is increasing, the supply voltages of the recent semiconductor integrated circuit devices decrease and each of the semiconductor devices has a plurality of different supply voltages. Such a semiconductor device has a level shift circuit connected between circuits which operate on different supply voltages. The level shift circuit is required to stably operate even on a low supply voltage.
FIG. 1
is a circuit diagram of a conventional level shift circuit
50
. An inverter circuit
1
is connected to a second voltage supply (PS
2
: GND) and a third voltage supply PS
3
having a third voltage (VD
3
: for example, 1 V) higher than a second voltage (VD
2
: 0 V) of the second voltage supply, and receives an input signal IN. The output terminal of the inverter circuit
1
is connected to the gate of an N channel MOS transistor (first transistor) Tr
1
. The first transistor Tr
1
has a drain connected to the drain of a P channel MOS transistor (second transistor) Tr
2
and a source connected to the ground GND. An output signal OUT is output from the drains of the first and second transistors Tr
1
and Tr
2
.
The input signal IN is supplied to the gate of an N channel MOS transistor (third transistor) Tr
3
whose drain is connected to the drain of a P channel MOS transistor (fourth transistor) Tr
4
and whose source is connected to the ground GND.
For example, 3 V of a first voltage supply PS
1
is supplied to the sources of the second and fourth transistors Tr
2
and Tr
4
. The gate of the second transistor Tr
2
is connected to the drain of the fourth transistor Tr
4
whose gate is connected to the drain of the transistor Tr
2
.
In the level shift circuit
50
, when the input signal IN has an H level (about 1 V), the inverter output signal of the inverter circuit
1
has an L level (nearly ground level: 0 V). When the inverter output signal has the L level, the first transistor Tr
1
and the fourth transistor Tr
4
are off. At this time, the third transistor Tr
3
is enabled, thereby enabling the second transistor Tr
2
. As a result, the voltage of the output signal OUT is approximately equal to the first voltage VD
1
(3 V).
When the input signal IN has an L level, the inverter output signal has an H level (nearly 1 V). The first transistor Tr
1
is enabled in response to the H-level inverter output signal. Therefore, the voltage of the output signal OUT is approximately “0” V.
The level shift circuit
50
therefore generates the output signal OUT which changes between the first voltage VD
1
(3 V) and “0” V in accordance with the input signal IN that changes between the third voltage VD
3
(1 V) and “0” V. The level shift circuit
50
is an interface circuit connected between a circuit which operates on the first voltage VD
1
and a circuit which operates on the third voltage VD
3
.
In the level shift circuit
50
, when the first transistor Tr
1
is off, the second transistor Tr
2
is enabled, so that the drain-source voltage of the first transistor Tr
1
is about 3 V (first voltage VD
1
). When the third transistor Tr
3
is off, the fourth transistor Tr
4
is enabled, so that the drain-source voltage of the third transistor Tr
3
is about 3 V.
Therefore, the first and third transistors Tr
1
and Tr
3
are high breakdown voltage transistors that can endure the drain-source voltage of 3 V. By way of contrast, the transistors of the inverter circuit
1
are low breakdown voltage transistors that can endure the drain-source voltage of approximately 1 V (the third voltage VD
3
).
As indicated by a transistor characteristic in
FIG. 2
, however, the high breakdown voltage transistors are enabled by a higher gate-source voltage than the low breakdown voltage transistors. In a case where the third voltage VD
3
is relatively low, therefore, the third transistor Tr
3
may not be enabled sufficiently even when the input signal IN changes to an H level. Alternatively, the first transistor Tr
1
may not be enabled sufficiently by the H-level inverter output signal. In this case, it is not possible to surely invert the output signal OUT.
In a case where the first and third transistors Tr
1
and Tr
3
are replaced with low breakdown voltage transistors, the first and third transistors Tr
1
and Tr
3
surely operate in accordance with the input signal IN and the inverter output signal. When the first and third transistors Tr
1
and Tr
3
are off, however, the first voltage VD
1
is applied between the drain and source of each of the first and third transistors Tr
1
and Tr
3
. In a case where the first voltage VD
1
exceeds the breakdown voltage of the first and third transistors Tr
1
and Tr
3
, therefore, the first and third transistors Tr
1
and Tr
3
may be broken.
SUMMARY OF THE INVENTION
Accordingly, it is a primary objective of the present invention to provide a level shift circuit which surely shifts the level of a low-voltage input signal by using high breakdown voltage elements, and a voltage generating circuit which is a constituting element of the level shift circuit.
To achieve the above object, the present invention provides a voltage generating circuit, connected between a first voltage supply having a first voltage and a second voltage supply having a second voltage lower than the first voltage, for generating at least one intermediate voltage between the first voltage and the second voltage. A plurality of voltage dividing elements is connected in series between the first voltage supply and the second voltage supply, for voltage-dividing a potential difference between the first voltage and the second voltage to generate the at least one intermediate voltage. The plurality of voltage dividing elements include a control MOS transistor which has a gate terminal and changes the at least one intermediate voltage in response to a gate voltage supplied to the gate terminal. The at least one intermediate voltage is generated at a node between adjoining two of the plurality of voltage dividing elements.
A further perspective of the present invention is a level shift circuit, connected to a first voltage supply having a first voltage, a second voltage supply having a second voltage lower than the first voltage and a third voltage supply having a third voltage higher than the second voltage and lower than the first voltage, for shifting a voltage of an input signal. An input inverter circuit is connected to the second and third voltage supplies, for receiving the input signal and inverting the input signal to thereby generate a first inverter signal. A voltage generating circuit is connected to the input inverter circuit, for voltage-dividing the first voltage in accordance with the first inverter signal to thereby generate an intermediate voltage. An output inverter circuit is connected to the first voltage supply, the second voltage supply and the voltage generating circuit, for generating a level shift output signal in accordance with the intermediate voltage.
A further perspective of the present invention is a level shift circuit, connected a first voltage supply having a first voltage, a second voltage supply having a second voltage lower than the first voltage and a third voltage supply having a third voltage higher than the second voltage and lower than the first voltage, for shifting a voltage of an input signal. An input inverter circuit is connected to the second and third voltage supplies, for receiving the input signal and inverting the input signal to thereby generate a first inverter signal. A voltage generating circuit is connected to the first voltage supply, the second voltage supply and the input inverter circuit, for voltage-dividing the first voltage in accordance with the first inverter signal to thereby generate at least one intermediate voltage. A level shift inverter circuit is connected to the voltage
Arent Fox Kintner Plotkin & Kahn
Fujitsu Limited
Nu Ton My-Trang
LandOfFree
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