Data processor architecture and instruction format for...

Details Data processor architecture and instruction format for... Data processor architecture and instruction format for...

1999-06-16

2003-01-21

Malzahn, David H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S523000, C712S221000

Reexamination Certificate

active

06510444

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to data processors, and more particularly to a data processor architecture and instruction format for increased efficiency.
BACKGROUND OF THE INVENTION
In data processing integrated circuits there is a trade-off between programmability and semiconductor area. In particular in the digital signal processing (DSP) area, a general purpose DSP processor may require a large amount of semiconductor area which is used for address generation, instruction decoding and sequencing, and data buffering. Alternatively, a hardware customized DSP may be small in semiconductor area but is usually lacking the flexibility provided by a general purpose DSP processing. A new data processor architecture and instruction format that better balances the programmability vs. semiconductor area trade-off would be valuable.


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