Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-12-29
2003-01-07
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S003000, C438S240000, C438S785000
Reexamination Certificate
active
06503810
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a capacitor for semiconductor devices, and more particularly, to a method for fabricating capacitors for semiconductor devices that provide the increased levels of capacitance necessary for more highly integrated devices, wherein a dielectric layer is formed of a material having a large dielectric constant and a stable stoichiometric structure.
2. Description of the Related Art
Recently, as the level of integration in semiconductor devices increases, research and development on semiconductor devices have been directed toward both reducing the cell area and reducing the device operating voltage. Although high levels of device integration greatly reduces the wafer area available for capacitor formation, the charge capacity preferred for operation of a memory device remains on the order of at least 25 fF per cell despite the reduction in cell area. This level of charge is useful in preventing the generation of soft errors and avoiding reductions in the refresh time.
To obtain sufficient capacitance values, conventional DRAM capacitors commonly use a dielectric film having a stacked nitride/oxide (NO) structure or an oxide-nitride-oxide (ONO) structure; a three-dimensional lower electrode structure, such as a cylinder; and/or reduced dielectric thickness. Despite these measures, however, the NO and ONO dielectric are generally unable to provide sufficient capacitance within the cell dimensions required for highly integrated (256M and above) semiconductor devices. Accordingly, efforts to increase the capacitance values have sought to replace the conventional oxide layer, the NO dielectric layer or the ONO dielectric layer with a metal based dielectric layer, such as Ta
2
O
5
or BST (BaSrTiO
3
) that provide a significantly increased dielectric constant (&egr;) in the range of approximately 20 to 25.
In particular, in DRAM designs using a nitride-oxide (NO) structure as the dielectric film, it has been typically necessary to utilize electrode structure having hemispherical grains (HSGs) formed on the surface of the storage electrode of the DRAM. The three-dimensional electrode structures with the hemispherical grain surfaces increase the effective surface area of the electrode to obtain the necessary capacitance values by increasing the height and vertical surface area of the electrode. However, increasing the height of the capacitor causes a step difference between the cell area and peripheral circuit area. Such step difference in turn introduces focal depth problems which compromise accuracy in the subsequent pattern formation process steps, such as photolithography and etch processes, that are usually performed after an interconnection process in the manufacture of semiconductor devices. Therefore, conventional capacitors formed of the NO layer have limitations in applications for 256 megabytes or greater future generation DRAMs that require a large capacitance.
In order to overcome such limitations as one described above associated with capacitors having a NO dielectric layer, active research and development are being conducted in designing capacitors with a Ta
2
O
5
layer, which has a large dielectric constant. However, a nominal Ta
2
O
5
film has an unstable stoichiometry that inevitably generates Ta atoms with oxygen vacancies in the thin dielectric layer due to the unbalanced composition ratio between the Ta and O atoms within the film. Accordingly, there is a need to stabilize the Ta
2
O
5
layer by oxidizing Ta atoms existing in the thin dielectric layer, thereby preventing the generation of a leakage current in the capacitor.
Additionally, the Ta
2
O
5
film is highly reactive with both doped polysilicon and metal based materials, such as titanium nitride (TiN), two materials commonly used to form the plate electrode and storage electrode adjacent the dielectric layer. As a result, oxygen present in the Ta
2
O
5
thin film may react with the electrode materials, thereby forming a low dielectric oxide layer at the interface and degrading the uniformity and electrical properties of the resulting capacitor.
During the formation of the Ta
2
O
5
layer, the organic portions from Ta(OC
2
H
5
)
5
—which is a precursor compound for Ta
2
O
5
—can reacts with O
2
or N
2
O gas to form various impurities such as carbon (C) atoms, carbon compounds including CH
4
and C
2
H
4
, and water vapor (H
2
O) in the Ta
2
O
5
layer. As a result of such impurities, as well as other ions or radicals present in the Ta
2
O
5
film, the resulting capacitors tend to exhibit increased leakage current and degraded dielectric characteristics.
SUMMARY OF THE INVENTION
To solve the above problems and limitations experienced with and/or inherent in prior art processes and materials, it is an object of the present invention to provide a method for forming a capacitor for semiconductor devices, which ensures sufficient capacitance to support advanced, high-density semiconductor devices.
In one embodiment, the present invention provides a method for forming a capacitor for semiconductor devices, the method comprising: preparing a semiconductor wafer; forming a storage electrode with a conductive layer on the semiconductor wafer; forming a dielectric layer with a Li
x
Ta-
1−x
O
3
layer having a perovskite structure on the storage electrode, where X=0.25-0.75; and forming a plate electrode including at least one conductive layer on the dielectric layer.
In another embodiment, the present invention provides a method for forming a capacitor for semiconductor devices, the method comprising: preparing a semiconductor wafer; forming a storage electrode with a conductive layer on the semiconductor wafer; performing nitridation on the surface of the storage electrode; forming a dielectric layer with a Li
x
Ta
1−x
O
3
layer having a perovskite structure on the storage electrode, where X=0.25-0.75; and forming a plate electrode including at least one conductive layer on the dielectric layer.
The present invention will become better understood in light of the following detailed description, the accompanying figures and the appended claims. The figures are provided by way of illustration only and are not intended to limit the scope of the invention.
REFERENCES:
patent: 4130694 (1978-12-01), Glass et al.
patent: 6054331 (2000-04-01), Woo et al.
patent: 6094292 (2000-07-01), Gerouki
patent: 6194754 (2001-02-01), Aggarwal et al.
patent: 59045999 (1982-06-01), None
patent: 06151762 (1992-11-01), None
patent: 06151762 (1994-05-01), None
Huynh Yennhu B.
Hyundai Electronics Industries Co,. Ltd.
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