Self-aligned field extraction grid and method of forming

Details Self-aligned field extraction grid and method of forming Self-aligned field extraction grid and method of forming

2002-02-08

2003-04-29

Smith, Matthew (Department: 2812)

Semiconductor device manufacturing: process

Electron emitter manufacture

C438S020000, C438S030000, C257S072000, C345S082000

Reexamination Certificate

active

06555402

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to grids and their formation, and more particularly to field extraction grids and their construction for field emission displays.
BACKGROUND OF THE INVENTION
In the microelectronics industry, there is a movement toward creating flat panel displays. These displays have the advantage of being significantly more compact than cathode ray tube displays, e.g., conventional computer monitors. There are different types of flat panel displays, such as liquid crystal displays (“LCDs”), gas-plasma displays, thin film transistor (“TFT”) displays, and field emission displays (“FEDs”). FEDs are particularly well suited to applications requiring high resolution, low power demand, wide viewing angle, and physical robustness in an operational environment.
FEDs are able to achieve high resolution owing in part to the presence of a significant number of emitter tip structures concentrated in a small space. These emitter tip structures, or cold cathode field emitter tip structures, and their formation are described in U.S. Pat. Nos. 5,391,259, 5,372,973, 5,358,908, 5,151,061, 3,755,704, 3,665,241, among others.
For emitter tip structures to emit electrons, a voltage bias is applied across the emitter tip structures and an extraction grid to create a potential difference therebetween. In U.S. Pat. No. 5,372,973 to Doan et al., formation of an extraction grid self-aligned to emitter tip structures is described.
In Doan et al., after forming emitter tip structures, a silicon nitride layer is deposited over the emitter tip structures. This layer is conformal to the surface upon which it is deposited. Next, boro-phospho-silicate-glass (“BPSG”) is deposited as an insulating layer. The BPSG layer is deposited and re-flowed, such that it does not extend above the silicon nitride layer. In other words, the silicon nitride layer above the emitter tip structures is left exposed after deposition and re-flowing of the BPSG. Next, a conductive layer, such as a layer of polysilicon having impurities (“dopants”), is deposited on the BPSG layer and the exposed regions of the silicon nitride layer. The layer of polysilicon is chemically-mechanically polished to re-expose regions of the silicon nitride layer; specifically, those regions disposed above apexes of the emitter tip structures. Accordingly, the polished conductive layer of polysilicon forms an extraction grid self-aligned to the emitter tips. The assembly may then be etched to pull the silicon nitride and the BPSG away from the emitter tip structures.
Though Doan et al. provide a self-aligned process for forming an extraction grid after formation of emitter tip structures, Doan et al. exposes the extraction grid layer to water, chemical-mechanical-polishing (CMP) slurry, and other potentially corrosive materials, some of which must then be cleaned off the assembly with other materials which may be harmful to some emitter structures.
A technique known as “etch back” is an alternative to CMP in situations where a blanket flow fill layer is previously deposited. Etch-back typically refers to a blanket plasma (“dry”) etch of such a surface. Etch-back does not have the above-mentioned disadvantages of CMP. However, etch-back uniformly removes material across a surface. Referring to U.S. Pat. No. 5,266,530 to Bagley, et al. (“Bagley”), dielectric layer
24
is etched back to expose a portion of underlying dielectric layer
22
. Dielectric layer
22
may then be etched to pull it away from tip
18
. Gate layer
26
may then be deposited, and subsequently etched to remove a portion of gate layer
26
deposited on tip
18
. In Bagley, uniform removal by etching is employed. However, it would be desirable to define a gate layer with fewer etching steps than Bagley.
Accordingly, it would be desirable in the art of manufacturing field emission devices to provide a self-aligned process for forming an extraction grid after forming emitter tip structures with the advantages associated with dry etch with conformal or substantially conformal (with plus or minus 50 nm) deposit material using fewer etch steps than in Bagley.
SUMMARY OF THE INVENTION
The present invention provides a method for forming a grid. In particular, a substrate assembly having one or more emitter tip structures formed thereon or therefrom is provided. An insulative layer is formed on or above the emitter tip structures, as well as on or above an associated emitter layer from which the emitter tip structures protrude. A conductive layer is formed on or above the insulative layer. An exposed surface of the conductive layer thus exhibits topographical variation owing to the presence of the underlying emitter tip structures. The exposed surface is then subjected to particle bombardment from ion milling. These particles are used to remove material from the conductive layer at various etch rates dependent at least in part on angle of incidence thereof. More particularly, portions of the conductive layer in near proximity to the one or more emitter tip structures are removed more rapidly than other portions. Accordingly, the insulative layer may be exposed in near proximity to the one or more emitter tip structures, while leaving a surrounding portion of the conductive layer for forming the grid.
In another embodiment, a field emission display comprises a substrate assembly including a plurality of vertical extending emitter tip structures, a face plate located vertically above the emitter tip structures, and an extraction grid location between the substrate assembly and the face plate. The extraction grid comprises a conductive material having plurality of openings aligned with the emitter tip structures to vertically expose the emitter tip structures to the face plate. The plurality of openings are formed by an ion milling operation responsive to topographical variations of the conductive material.


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