Pulse or digital communications – Testing – Phase error or phase jitter
Reexamination Certificate
1999-04-28
2003-03-11
Chin, Stephen (Department: 2634)
Pulse or digital communications
Testing
Phase error or phase jitter
C375S371000, C375S376000
Reexamination Certificate
active
06532257
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method for performing phase comparison, two binary signals being compared in the method by means of two asynchronous state machines, two output signals being generated by means of the same machines to control a phase.
The invention also relates to a phase comparator comprising two asynchronous state machines, which are arranged to generate two output signals to control a phase.
BACKGROUND OF THE INVENTION
A digital phase comparator is needed in the operation of for instance a phase locked loop. A phase locked loop is used in applications where a clock signal is synchronized with an external signal. A typical application is a digital radio system receiver in which the receiver synchronizes with a received signal to detect the signal.
There are various prior art phase comparator solutions. The most common solution comprises logical circuits and feedback, which function either synchronically or asynchronically. Patent EP 520 558, which will be included herein as a reference, discloses a phase comparison circuit solution comprising logical gates. In order to avoid transients, the operation of the logical circuits of the phase comparator is secured by using delay means, which are also logical gates. Transients, which occur when both of the input signals change simultaneously, are most harmful to the reliable operation of asynchronous circuits. It is not, however, desirable to use delay means when transients are to be avoided because the use of delay means requires, for instance, particularly careful circuit layout design.
SUMMARY OF THE INVENTION
An object of the invention is thus to provide a method and an equipment implementing the method to allow the above mentioned problems to be solved and the use of delay means to be avoided.
This is achieved with a method described in the preamble, characterized in that two asynchronous, functionally similar state machines are used in the method, whereby to a first state machine are fed: a first signal to be compared, an output signal of a second state machine and a handshaking signal of the second state machine, and to the second state machine are fed: a second signal to be compared, and output signal of the first state machine and a handshaking signal of the first state machine; that the first state machine activates its handshaking signal after having detected that the first signal to be compared is activated; that the second state machine activates its handshaking signal after having detected that the second signal to be compared is activated, the handshaking signal ensuring the logical operation of the method; and that, to activate the output signal detecting a phase difference in and controlling a phase of the first state machine, the following steps are taken: checking of the state of the first signal to be compared, the state of the output signal of the second state machine and the state of the handshaking signal of the second state machine; and that, to activate the output signal detecting a phase difference in and controlling a phase of the second state machine, the following steps are taken: checking of the state of the second signal to be compared, the state of the output signal of the first state machine and the state of the handshaking signal of the first state machine.
A phase comparator of the invention, in turn, is characterized in that the state machines are functionally similar, the first state machine having as input signals the first signal to be compared, the output signal of the second state machine and the handshaking signal of the second state machine; the second state machine having as input signals the second signal to be compared, the output signal of the first state machine and the handshaking signal of the first state machine; that the first state machine is arranged to generate its handshaking signal from an active edge of the first signal to be compared and the second state machine is arranged to generate its handshaking signal from an active edge of the second signal to be compared, the handshaking signals securing the logical operation of the phase comparator by detecting the active edge of each of the signals to be compared; and that, to activate the output signal detecting a phase difference in the first state machine, the first state machine is arranged to: check the state of the first signal to be compared, the state of the output signal of the second state machine and the state of the handshaking signal of the second state machine; and that, to activate an output signal detecting a phase difference in the second state machine, that second state machine is arranged to: check the state of the second signal to be compared, the state of the output signal of the first state machine and the state of the handshaking signal of the first state machine.
The method and the phase comparator provide various advantages. The solution of the invention allows separate delay means to be disposed of and the solution is well suited for digital asic circuits. The operation is secured by means of a handshaking mechanism. In addition, the structure is symmetrical, providing thus similar timings for each of the input signals and each of the output signals.
REFERENCES:
patent: 4814726 (1989-03-01), Byrd et al.
patent: 5291529 (1994-03-01), Crook et al.
patent: 5583458 (1996-12-01), Bazes
patent: 5744983 (1998-04-01), Bazes
patent: 5920207 (1999-07-01), Suresh
patent: 6239626 (2001-05-01), Chesavaage
patent: 3130156 (1983-02-01), None
patent: 3813550 (1989-03-01), None
patent: 0520558 (1992-12-01), None
patent: WO 97/23047 (1997-06-01), None
Chin Stephen
Fan Chieh M.
Nokia Telecommunications Oy
Pillsbury & Winthrop LLP
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