Fractional synthesizer comprising a phase jitter compensation

Details Fractional synthesizer comprising a phase jitter compensation Fractional synthesizer comprising a phase jitter compensation

2001-04-09

2003-04-08

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S015000

Reexamination Certificate

active

06545548

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a synthesizer with fast acquisition time and low phase noise using the principle of fractional division in implementing a technique of compensation for phase jitter suited to low voltage operation and minimum power consumption.
It relates for example to synthesizers working at a low and single voltage of 2.7 V and is compatible with ASIC technology and integration, again for minimum power consumption.
Advantageously, synthesizers of this kind can be used to obtain channel links compatible with radio-telephone equipment, especially equipment complying with the GSM and GPRS norms.
The invention can also be applied in any device integrating a frequency synthesis under constraints of low voltage and minimum power.
2. Description of the Prior Art
The prior art discloses frequency synthesizers having very short frequency acquisition times and very high frequency resolution values. The synthesizer developed by Philips under the catalog reference SA 8025 is an example.
However, the comparison frequencies commonly used are generally not compatible with the spectral characteristics required and cannot be used to obtain the desired acquisition times in a framework of applications operating under low voltage and minimum power.
It has been shown that, in fractional division synthesis, the phase error difference in the phase comparator is proportional to:
the value Pk (dynamic phase error) contained in the phase accumulator, and
the period Ts=1/Fs of the synthesized signal Fs.
The value Pk is variable and known at each reference period Tr as well as Fs. If Fr is the reference frequency, it is enough, at each reference period 1/Fr, to prepare a signal proportional at all times to these two quantities in order to compensate for this phase error. Since the phase error is different at each reference cycle, the correction period must be substantially smaller than 1/Fr.
Various approaches have been proposed to minimize or even eliminate the phase jitter lines due to fractional synthesis. One approach consists in carrying out a current weight correction modulated in duration (the compensation signal Ic has both an intensity and a duration that are a function of the value given by a phase accumulator) as described in the patent application FR 2.557.401 by the Applicant. The fractional division synthesizer with low phase jitter described in this patent comprises several current sources that are summated in taking account of the temperature and linearity before being sent to an integrator. The synthesizer comprises an operational amplifier supplied with two high voltages, a positive voltage and a negative voltage and a digital-analog converter or DAC controlling the current sources. The feedback control voltage is sampled by a sample-and-hold circuit before it is sent to the oscillator control.
A device of this kind, although it reduces the phase jitter, cannot be applied to high-speed, low-consumption applications, especially low voltage applications (whether unique or not) such as the GSM.
It is also difficult to apply zero voltage to the summation node of the different current sources, whatever the control voltage of the oscillator and the temperature dissipated in the circuit. Indeed, when the control voltage of the oscillator varies, the voltage at the summation node of the current source also varies because of the lack of precision of the prepositioning. These leads to a modification of the point of operation of the feedback control amplifier which then causes a modification in the correction current.
SUMMARY OF THE INVENTION
The present invention proposes a simple and efficient way of obtaining compensation for phase jitter due to fractional synthesis.
The invention relates to a multiple fractional division frequency synthesizer comprising a frequency generator, a voltage-controlled oscillator, a programmable variable N-divider, a phase comparator, an integration and filter circuit, a time window generator, a weighted current source, a phase accumulator, a charge-pump circuit comprising several transistors.
The invention is characterized in that said current source is connected to said charge-pump circuit so as to directly switch the currents over to the emitter of one or more transistors of the charge-pump circuit.
The synthesizer is, for example, powered by a low voltage substantially equal to 2.7 V.
The charge pump circuit may comprise at least:
a one transistor Q
3
whose emitter is connected to a resistor Rc, itself linked with the phase comparator,
one transistor Q
2
in which there flows the charging current Ic, linked with the integration circuit, and
one transistor Q
4
having its emitter connected to a resistor Rp connected to the phase comparator and its collector connected to the integration circuit, the discharging current Ip flowing through Rp and Q
4
, and the weighted current source comprises one or more parallel-mounted resistors R
1
, R
2
, R
3
, said resistor or resistors being connected to the emitter of Q
3
and to at least one field-effect transistor Q
5
, Q
6
, Q
7
receiving, at their gates, the value or values Pk contained in the phase accumulator, the source of the field-effect transistors being linked with the time window generating, during a time Tcor, a low level signal or “0V” signal.
According to another embodiment, the charge-pump circuit comprises for example:
a transistor Q
3
whose emitter is connected to a resistor Rc itself linked with the phase comparator,
a transistor Q
2
in which there flows the charging current Ic, linked with the integration circuit, and
a transistor Q
4
having its emitter is connected to a resistor Rp linked with the phase comparator and its collector linked with the integration circuit, the discharging current Ip flowing through Rp and Q
4
, and a transistor Q
5
having its base connected to the base of the emitter Q
3
, its collector linked to the base of Q
1
and its emitter linked to a resistor Rcor, the resistor Rcor being linked to the device generating a low-level “0V” signal during a correction time Tcor.
The invention also relates to a fractional division frequency synthesizer with fast acquisition time and low phase noise having at least one of the characteristics given here above.
The invention also relates to a radiocommunications device comprising at least one emitter and one receiver and a fractional division frequency synthesizer comprising at least one of the above characteristics.
The invention also relates to a method for synthesizing a frequency comprising at least one of the following steps:
using a frequency synthesis loop comprising a programmable variable N-divider, a charge-pump circuit, a current source and a time window generator,
coupling an output of the current source to said charge-pump circuit in order to directly switch the correction current or currents over to the emitter of at least one of the transistors of the charge-pump circuit,
generating a signal from the low-level “0” time window and applying it to the current source during a period &Dgr;Tcor.
The method and the device according to the invention can be applied for example in the field of GSM and/or GPRS.
The synthesizer according to the invention has especially the following advantages:
it reduces the phase noise in the passband of the synthesizer by at least 10 dB for constant technology, for example the ASIC technology,
it allows the least possible deterioration in the quality of the phase noise delivered at the output of the charge-pump function,
it keeps its efficiency throughout the synthesized frequency range,
it offers the possibility of using only one power voltage which can drop to 2.7 V.


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patent: 5495206 (1996-02-01), Hietala
patent: 5557090 (1996-09-01), Ganne et al.
patent: 5592120 (1997-01-01), Palmer et al.
patent: 5663686 (1997-09-01), Tada
patent: 5752175 (1998-05-01), Roullet et al.
patent: 5818303 (1998-10-01), Oishi et al.
patent: 6107843 (2000-

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