Ballast layer for field emissive device

Details Ballast layer for field emissive device Ballast layer for field emissive device

2000-02-03

2003-01-14

O'Shea, Sandra (Department: 2875)

Electric lamp and discharge devices

With luminescent solid or liquid material

Vacuum-type tube

C313S497000, C313S309000, C313S336000, C313S351000

Reexamination Certificate

active

06507145

ABSTRACT:

BACKGROUND AND SUMMARY OF INVENTION
The present invention is directed to a ballast layer for field emissive device (FED) flat displays. The field emissive device used in FED displays is a point emitter that emits a flow of electrons in a vacuum under the influence of a moderate extraction voltage. Point emitters are based either on (1) field emission, in which a large field is generated by a very sharp angle at the tip of the emitter, or (2) special low work function materials such as diamond.
A pixel of an FED display is made of a large number of adjacent point emitters operating in parallel to cover the full surface of the pixel. One of the key problems in the design of such a display is that a point emitter tends to operate with a “negative” resistance. Thus, when a set of emitters run in parallel, they tend to have an arc-like behavior (i.e., one emitter takes over all the current and the other emitters are inhibited). A solution to this problem was proposed by A. Ghis et al.,
IEEE Transactions
on electron devices, Vol. 38, No. 10 (October 1991). This solution is based on a resistive ballast layer that interconnects the emitters and the source line. The added series resistance compensates for the negative resistance of the point emitters, thereby allowing a stable, parallel operation of adjacent point emitters.
The ballast layer, however, is particularly difficult to manufacture. The required resistivity for the ballast layer in an FED is in the range of 10
2
to 10
5
Ohm centimeter, corresponding to a conductivity (&sgr;) of less that 10
−2
Ohm cm
31 1
. This range of resistivity is too large to be achieved with conventional metal alloys. Although this range of conductivity can be achieved by lightly-doped semiconductors, these materials are very sensitive to minute fluctuations of doping levels and are very difficult to use for a stable production.
U.S. Pat. No. 5,789,851 describes obtaining a controlled resistance using a resistive layer comprising doped amorphous silicon film alloyed with another element, such as carbon or phosphorous. U.S. Pat. No. 5,789,851 also describes a way of manufacturing a ballast layer in a controlled manner compatible with production.
However, a new specification was introduced by the FED industry that makes the ballast layer design even more difficult to achieve. It is now required for the ballast layer to have the same type of sheet resistance over the full range of operating temperatures that occur for the most demanding FED display users (e.g., the car industry or military applications). This temperature range is typically within the range of −50° C. to 100° C. Thus, the resistance which a ballast layer introduces in an emitter circuit should vary by no more than a factor 3-6 over the −50 to +100° C. temperature range (e.g., &sgr;(90° C.)/&sgr;(−50° C.)<5). This requirement adds to the constraint on the ballast layer resistivity. The square resistance of the ballast layer should be larger than a few megaOhm. Thus, the material resistance of a 300 nm ballast layer, for example, is in excess of 100 Ohm centimeter.
Unfortunately, semiconductors are known to have a rather large variation of conductivity with temperature, and this new specification for the ballast layer severely increases the difficulty in ballast layer design. Conductivity increases rapidly with temperature (at least in the range of −50° C. to 100° C.) according to the general relation:
&sgr;=&sgr;
0
exp(−
E
a
/kT
)
where &sgr; is conductivity; k is the Bolzmann constant; T is absolute temperature; and E
a
is the activation energy, which is generally related to the position of the Fermi level in the particular semiconductor. The activation energy can vary strongly in a given semiconductor with the doping level. Basically, an intrinsic (or compensated) material is rather resistive and has a rather large activation energy (of the order of half of the semiconductor forbidden band gap). In contrast, a doped material has a small activation energy, but is rather conductive.
The relative variations of the conductivity of a semiconductor over the −50 to +100° C. temperature range are shown in FIG.
2
. The acceptable variation should remain below the threshold. As illustrated in
FIG. 2
, the conductivity variation is within the requirement for FED manufacturing only for an activation energy well below 0.1 eV. This value of activation energy is very low and, as known in the silicon industry, corresponds to very high level of doping, for example a doping concentration of 3×10
17
cm
−3
or above. Sze,
Physics of Semiconductor Devices,
pages 37 and 43 (1969). For an doping concentration above 3×10
17
cm
−3
, the resistivity of silicon is lower than 0.2 Ohm cm for p-type Si and lower than 0.05 Ohm cm for n-type Si. However, in both cases, the doped silicon is more than 500 times too conductive with respect to the estimated specification for FED applications.
Thus, semiconductors such as silicon cannot meet the specifications of (1) a conductivity of less than 10
−2
Ohm cm
−1
and (2) a variation of resistance corresponding to &(90° C.)/&(−50° C.) less than 5.
FIG. 3
shows the evaluation of many different types of amorphous (a-Si:H) silicon, nanocrystalline silicon, and silicon-carbon alloys. G. Lucovsky and C. Wang,
Mat. Res. Soc. Symp. Proc.,
page 377, Vol. 219 (1991). As illustrated in
FIG. 3
, the data form a scattered cloud of points in a plot of activation energy against resistivity at room temperature. Two model curves are also shown in FIG.
3
. All of the materials are far away from the zone of interest for FED applications, either because the material is too conductive (by more than a factor 20), or because the material has too much temperature variation for its conductivity (activation energy in excess of 0.18 eV). Among the thin films based on plasma-enhanced chemical vapor deposition (PECVD) deposited silicon, only nanocrystalline films with strong doping (e.g., n-doped films with PH
3
based doping) achieve an activation energy below 0.1 eV. Unfortunately, the conductivity of such film is 30 to 100 times larger than the smallest conductivity required for FED applications.
The problem is that low activation energy and high conductivity always occur together for semiconductors. The FED ballast layer application runs into a very basic problem intrinsic to the semiconductor structure. The ballast layer according to the present invention solves this problem.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.


REFERENCES:
patent: 5789851 (1998-08-01), Turlot et al.
patent: 5852346 (1998-12-01), Komoda et al.
patent: 6060743 (2000-05-01), Sugiyama et al.
patent: 6064149 (2000-05-01), Raina
patent: 6137214 (2000-10-01), Raina
patent: 6139385 (2000-10-01), Raina

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