Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
2002-06-20
2003-09-16
Marcelo, Melvin (Department: 2663)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S516000, C709S248000
Reexamination Certificate
active
06621832
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to data communications and, more particularly, to a method for controlling isochronous data communications within a digital system having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus.
BACKGROUND
The components of a computer or other digital system are typically coupled to a common bus for communicating information to one another. Various bus architectures are known in the prior art, and each bus architecture operates according to a communications protocol that defines the manner in which data transfer between components is accomplished.
The Institute of Electrical and Electronic Engineers (IEEE) has promulgated a number of different bus architecture standards including IEEE standards document 1394, entitled
Standard for a High Performance Serial Bus
(hereinafter “IEEE-1394 Serial Bus Standard”). A typical serial bus having the IEEE-1394 standard architecture is comprised of a multiplicity of nodes that are interconnected via point-to-point links, such as cables, that each connect a single node of the serial bus to another node of the serial bus. Data packets are propagated throughout the serial bus using a number of point-to-point transactions, wherein a node that receives a packet from another node via a first point-to-point link retransmits the received packet via other point-to-point links. A tree network configuration and associated packet handling protocol ensures that each node receives every packet once. The serial bus of the IEEE-1394 Serial Bus Standard may be used as an alternate bus for the parallel backplane of a computer system, as a low cost peripheral bus, or as a bus bridge between architecturally compatible buses.
A communications protocol of the IEEE-1394 Serial Bus Standard specifies two primary types of bus access: asynchronous access and isochronous access. Asynchronous access may be either “fair” or “cycle master”. Cycle master access is used by nodes that need the next available opportunity to transfer data. Isochronous access is used by nodes that require guaranteed bandwidth, for example, nodes transmitting video or audio data. The transactions for each type of bus access are comprised of at least one “subaction”, wherein a subaction is a complete one-way transfer operation.
In the case of, for example, digital video data transfers within digital systems conforming to the IEEE-1394 Serial Bus Standard, the video data may be transferred for example, between a mass storage device (e.g., a digital memory such as a hard disk drive, a flash memory device or other storage medium) and a digital video camera or other recorder (e.g., to store an edited video sequence) under the control of a computer processor or other device (e.g., a DMA controller). The video data is transferred as a series of frames, each frame being made up of a number of data packets. The individual data packets include a number header fields (which include various information regarding the data as well as addressing information) as well as the video data itself.
In order to ensure that each frame of the video data is played out in the proper sequence, the frames must be “time stamped” with an appropriate frame presentation time (e.g., measured in terms of “cycle time” of an isochronous transaction on a bus complying with the IEEE-1394 Serial Bus Standard) when they are recorded. The cycle time is maintained by a cycle master as described in the IEEE-1394 Serial Bus Standard. The frame presentation time for individual frames of data is recorded in a particular header field, referred to as an SYT field, of the first packet of each frame. In essence, the frame presentation time “stamped” in the SYT field of the packet header is an indication to the receiver of the time that the frame should be played out. For digital video data, the frame presentation time may be up to 450 &mgr;sec. in the future. That is, from the point of view of the receiver, the SYT field frame presentation stamp value for a given frame of data must be within 450 &mgr;sec. of the time the first packet in that frame is received. Thus, in the example given above, when the digital video data is transferred from the mass storage device to the recording medium, the computer processor or other device which is controlling the transfer must insert appropriate frame presentation time stamp (or SYT) values into the SYT fields of the first packet in each frame of the video data. Note that the 450 &mgr;sec. requirement is specific to video data and other types of data, e.g., MIDI audio data, may have other frame presentation time requirements.
Some cycle master capable devices, e.g., digital video cameras, have been known to have relatively low accuracy cycle times. This presents a problem when such a device is to act as the cycle master. For example, if the accuracy of the cycle master cycle timer falls below an acceptable standard, the time stamps recorded in the SYT fields of packets transmitted within the digital network will be affected. This, in turn, will affect the packet frame rate. If the packet frame rate fails to fall within acceptable limits for the particular type of video data transmission (e.g., an NTSC compatible transmission), color tracking of the video signal may be lost (e.g., at the monitor) and/or other consequences may result. Thus, what is needed is a means to compensate or correct for cycle master cycle timer inaccuracies.
SUMMARY OF THE INVENTION
Methods for controlling isochronous data communications within a digital system having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus are described. In one embodiment, a cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.
Other features and advantages of the present invention will be apparent from the detailed description and accompanying drawings which follow.
REFERENCES:
patent: 5751721 (1998-05-01), Bloks
patent: 5933430 (1999-08-01), Osakabe et al.
patent: 5991842 (1999-11-01), Takayama
patent: 6021505 (2000-02-01), Ayyagari et al.
patent: 6128318 (2000-10-01), Sato
patent: 6373821 (2002-04-01), Staats
patent: 6418150 (2002-07-01), Staats
“P1394 Standard For A High Performance Serial Bus”,The Institute of Electrical and Electronic Engineers, Inc., IEEE Standards Department,P1394 Draft 8.0v3, pp. 1-394 (Oct. 16, 1995).
Apple Computer Inc.
Blakely , Sokoloff, Taylor & Zafman LLP
Marcelo Melvin
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