Programmable logic array device with random access memory...

Details Programmable logic array device with random access memory... Programmable logic array device with random access memory...

2001-12-26

2003-04-29

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230010, C365S230080, C365S230060, C365S189020, C365S063000

Reexamination Certificate

active

06556500

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic array devices having embedded random access memory arrays which can be configured as programmable product-term-type logic elements if desired. More particularly, the invention relates to programmable logic devices having look-up tables for performing logic and larger blocks of random access memory which are usable by the user for such purposes as data storage and additional look-up table logic, and which larger blocks of random access memory are alternatively configurable as programmable product-term-type logic elements.
One known type of programmable logic device includes an array of programmable AND gates which typically produces multiple outputs, each generally resulting from the ANDing of multiple inputs. These AND gate array outputs are commonly referred to as “product terms” because the logical representation of the AND function is analogous to multiplication. Generally, a plurality of these product terms, or “p-terms,” are combined by an OR gate to produce a sum-of-products output (the OR function being analogous to addition).
Another type of programmable logic device is implemented using many relatively small look-up tables whose inputs are either the inputs of the programmable logic device or the outputs of other look-up tables in the device.
Programmable logic architectures have recently been developed in which relatively large, user-configurable blocks of random access memory (RAM) are provided among blocks of look-up-table-type programmable logic. One such architecture is described in Cliff et al. U.S. Pat. No. 5,689,195, which is hereby incorporated by reference herein in its entirety. These user-configurable memory blocks can be used as general-purpose memory for the device, or they can be used as additional relatively large look-up-table-type logic blocks.
Look-up-table-type logic may have a disadvantage relative to p-term-type logic with respect to the number of inputs to a logic function that can be implemented in one reasonably sized block of circuitry. For example, the above-mentioned Cliff et al. reference shows devices having many four-input look-up tables and several relatively large blocks of user-configurable RAM that can function as eight- to 11-input look-up tables. To perform logic functions of more than 11 inputs in such a device it is necessary to use a tree of the available look-up table units. It is not practical to redesign devices of this kind with larger user-RAM blocks to individually act as look-up tables having significantly larger numbers of inputs (e.g., 20, 30, or more inputs) because such RAM blocks would have to be extremely large. However, p-term-type logic arrays with 20, 30, or even more inputs are not excessively large and can therefore more readily provide outputs which are functions of large numbers of inputs.
In view of the foregoing, it is an object of this invention to provide look-up-table-type programmable logic devices with the capability of more readily performing some logic functions having large numbers of inputs.
It is another object of this invention to provide look-up-table-type programmable logic devices which include relatively large blocks of user-configurable RAM with the capability of optionally performing some logic functions using p-term-type logic in the user-configurable RAM if desired.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices having look-up-table-type logic and relatively large blocks of user-configurable RAM which are optionally usable to perform p-term-type logic. For storing data in a RAM block, or for using the RAM block as ordinary memory (including additional look-up table logic), circuitry is provided for addressing the various rows of the block one at a time on an individual basis. For using a RAM block to perform p-term-type logic, additional circuitry is provided for alternatively addressing multiple rows of the block in parallel. For each column of memory locations in a RAM block, the contents of the rows that are addressed in parallel are logically ANDed to produce a p-term output of the contents of those rows. OR logic circuitry is provided for selective use to logically OR various column outputs and thereby produce sum-of-products output signals when the RAM block is being used in p-term mode.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.


REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3849638 (1974-11-01), Greer
patent: 4195352 (1980-03-01), Tu et al.
patent: 4740917 (1988-04-01), Denis et al.
patent: 4876466 (1989-10-01), Kondou et al.
patent: 4912345 (1990-03-01), Steele et al.
patent: 4975601 (1990-12-01), Steele
patent: 5027011 (1991-06-01), Steele
patent: 5099150 (1992-03-01), Steele
patent: 5121006 (1992-06-01), Pedersen
patent: 5128559 (1992-07-01), Steele
patent: 5144582 (1992-09-01), Steele
patent: RE34363 (1993-08-01), Freeman
patent: 5270587 (1993-12-01), Zagar
patent: 5302865 (1994-04-01), Steele et al.
patent: 5362999 (1994-11-01), Chiang
patent: 5383146 (1995-01-01), Threewitt
patent: 5386155 (1995-01-01), Steele et al.
patent: 5408434 (1995-04-01), Stansfield
patent: 5450608 (1995-09-01), Steele
patent: 5473267 (1995-12-01), Stansfield
patent: 5532957 (1996-07-01), Malhi
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5557218 (1996-09-01), Jang
patent: 5559450 (1996-09-01), Ngai et al.
patent: 5559747 (1996-09-01), Kasamizugami et al.
patent: 5689195 (1997-11-01), Cliff et al.
patent: 5744980 (1998-04-01), McGowan et al.
patent: 5757207 (1998-05-01), Lytle et al.
patent: 5809281 (1998-09-01), Steele et al.
patent: 5812479 (1998-09-01), Cliff et al.
patent: 5815003 (1998-09-01), Pedersen
patent: 5828229 (1998-10-01), Cliff et al.
patent: 5848005 (1998-12-01), Cliff et al.
patent: 5883850 (1999-03-01), Lee et al.
patent: 6020759 (2000-02-01), Heile
patent: 6028808 (2000-02-01), Cliff et al.
patent: 6052327 (2000-04-01), Reddy et al.
patent: 6118720 (2000-09-01), Heile
patent: 6218860 (2001-04-01), Lytle et al.
patent: 6340897 (2002-01-01), Lytle et al.
patent: 6347061 (2002-02-01), Heile
C. Barre, “L'utilisation du FPLA; Evaluez les Applications d'un Composant Puissant qui Peut se Reveler trés Economique”, Electronique & Applications Industrielles, EAI 250, Apr. 1, 1978, pp. 21-25.
D. Bursky, “Combination RAM/PLD Opens New Application Options”, Electronic Design, May 23,1991, pp. 138-140.
“iFX8160 10ns FLEXlogic FPGA with SRAM Option; Advance Information”, Intel Corporation, Oct. 1993, pp. 2-47 through 2-56.
T. K-K. Ngai, “An SRAM-Programmable Field-Reconfigurable Memory”, Master of Applied Science degree thesis submitted to the Department of Electrical Engineering of the University of Toronto, 1994.
A. Stansfield et al., “The Design of a New FPGA Architecture”, Proceedings Field Programmable Logic (FPL) 1995, Springer Lecture Notes in Computer Science 975, pp. 1-14.
A. Kaviani et al., “Hybrid FPGA Architecture”, Proceedings 4th International Symposium on FPGAs (FPGA 96), Feb. 1996.
Reddy, S. et al. “A High Density Embedded Array Programmable Logic Architecture”, IEEE 1996 Custom Integrated Circuits Conference, May 5, 1996, pp. 251-254.
Brown, S. et al. “FPGA and CPLD Architecture: A Tutorial”, IEEE Design & Test of Computers, Jun. 1, 1996, pp. 42-57.
Nelson, R. “Embedded memory enhances programmable logic for complex, compact designs”, Electrical Design News (EDN), vol. 41, No. 23, Nov. 7, 1996, pp. 91, 92, 94, 96, 98, 100-102, and 106.
“Altera Enables System-Level Integration with Raphael Family of Embedded PLDs”, Altera Corporation, San Jose, California, Aug. 31, 1998.
“Apex 20K Programmable Logic Device Family; Advance Product Brief”, Altera Corporation, San Jose, California, Oct. 1998, pp. 1, 2, and, and 9.
“Altera Unveils New Name for Raphael: Advanced Programmable Embedded Matrix (APEX)”, Altera Corpor

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