Method of forming shallow trench isolation in a silicon wafer

Details Method of forming shallow trench isolation in a silicon wafer Method of forming shallow trench isolation in a silicon wafer

2000-11-14

2003-03-25

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S438000, C438S700000, C438S973000, C257S521000

Reexamination Certificate

active

06537895

ABSTRACT:

TECHNICAL FIELD
The present invention relates to forming a shallow trench isolation (STI), and more specifically to a method of aligning the STI regions to reduce defects in silicon.
BACKGROUND ART
Semiconductor integrated circuits chips are constructed as dies on wafers. A typical wafer material is crystalline silicon. Wafers are cut from single crystal silicon ingots grown from more impure polysilicon by means of Czochralski, CZ, crystal growth. In CZ growth, single crystal ingots are pulled from molten silicon contained in a crucible. Czochralski silicon wafers, CZ wafers, are preferred for VLSI applications since they can withstand high thermal stresses and are able to offer an internal gettering mechanism that can remove unwanted impurities from the device structures on a wafer surface. This also gives the wafer a uniform internal structure based on silicon's diamond cubic lattice structure. Although the diamond cubic lattice provides strength and rigidity to the wafer, imperfections in the crystal lattice can adversely affect the wafer electrical properties leading to a reduction in the number of good dies per wafer.
Silicon, Si, is a column IV element and has four valence electrons, each of these electrons is shared with one of its four nearest neighbor Si atoms. Each pair of valence electrons shared between nearest neighbors form a covalent bond giving silicon its solid crystalline structure. The diamond cubic lattice structure of silicon is depicted in FIG.
1
.
The crystal lattice structure of the wafer forms planes traversing it in multiple directions. Three principal planes are shown in FIG.
2
. The orientation of these planes (
111
), (
110
) and (
100
) within respective illustrative cubic structures
22
,
24
and
26
is shown. The direction of each plane is determined by taking a set of three vector components defining three axial directions x, y and z. All three cubes
22
,
24
and
26
are aligned along the three x, y and z axial directions, and each cubic face has a unit length of one. In this coordinate system, a one indicates which axis the plane traverses. For example, the plane defined by (
111
) is shown traversing all three axes x, y and z. Similarly, plane (
110
) traverses the x and y axes, and plane (
100
) traverses only the x axis.
Many structural properties of silicon depend on its planar orientation. Plane (
111
) has the highest density of atoms and is packed very tightly. The tighter a plane is packed, the higher the probability that slip dislocation will occur. These dislocations can promote charge leakage that can lead to device failure.
Therefore, it is important to be able to identify crystalline planes on a wafer. To help identify these planes, wafers are typically constructed with a primary flat region relative to a selected crystal orientation. The primary flat orientation is identified by X-rays techniques, and is used for several purposes. For example, automated wafer handling equipment utilizes the primary flat to obtain correct alignment, and devices on a wafer can be oriented to specific crystal directions using the primary flat as a reference.
Typically, the primary flat of the wafer is aligned with plane (
110
). As a consequence, some constructed devices may have dimensions that are aligned along the more tightly packed planes. This traditionally has not been a problem since any defects formed had little influence on device performance and could be ignored.
Nonetheless, not all defects can be ignored and several techniques for reducing specific defects have been proposed. U.S. Pat. No. 5,576,230 to Guldi explains that microscopic dislocations can occur in the drain and source regions of an MOS transistor if recrystallization after ion implantation is allowed to proceed along multiple crystalline planes. These microscopic dislocations can grow under the application of stress from overlayers. Guldi suggests that if the drain and source regions are implanted at an angle, recrystallization may be promoted along a single plane, specifically plane (
110
), and limit recrystallization along other planes.
Because of the relatively large dimensions of isolation regions, structural defects in the substrate along the isolation regions are of special concern. U.S. Pat. No. 5,913,133 to Lee et al. explains that damage can occur to an isolation region due to misalignment of a mask. Lee states that the damage can be reduced by forming the isolation layer so that the edge portion of the isolation layer is not exposed to the surface of the substrate. U.S. Pat. No. 5,904,538 to Jeong-Hwan Son et al. shows a method for developing shallow trench isolation regions, STI, in a semiconductor memory device by implanting fluorine ions in a semiconductor substrate where the trench is to be formed before forming the trench. Fluorine ions are diffused at opposing sides along the upper corners of the trench next to the substrate surface. The fluorine ions protect the isolation region from light exposure and thereby reduce damage.
These approaches attempt to reduce defects through specific changes to the IC fabrication process. Another approach to reducing defects is to improve the quality of the wafer itself. One method of doing this is through an epitaxial growth process that deposits a thin layer of single crystal material upon the surface of a single crystal substrate. Such wafers are known as epi wafers. Circuit structures can be constructed in a thin, lightly doped epitaxial layer over a heavily doped substrate. Experimentation with these types of wafers have shown that they have higher yields than standard polished wafers. Currently, however, wafers with an epitaxial substrate are more than twice as expensive as standard polish wafers and their benefit does not outweigh their high cost.
It is an object of the present invention to reduce defects, such as slip dislocation and gettering points for impurities, in an IC substrate.
It is another object of the present invention to improve isolation regions in a substrate with minimal increase in cost.
It is still another object of the invention to provide a process of constructing STI isolation regions that reduces defects due to the inherent crystalline structure of silicon.
SUMMARY OF THE INVENTION
Applicants have found that as device dimensions continue to shrink and thermal cycling continues to increase, substrate quality is becoming more critical to device performance. Trench formation, such as STI and LOCOS, causes significant stress concentration points, such as gettering points for impurity and other silicon defects.
It has been found that etching the wafer along plane (
110
) causes the STI islands to align themselves in both vertical and horizontal directions with plane (
111
). This effect results from the relative orientation of plane (
111
) to plane (
110
). As the trench is formed, its curvature aligns itself with plane (
111
). This alignment with plane (
111
) reduces the quality of the wafer since plane (
111
) is very tightly packed and susceptible to slippage and other dislocation defects.
It has been found that by moving the primary flat forming of a CZ wafer by 45° from plane (
110
) to plane (
100
), the trench formation will no longer be aligned with plane (
111
). In this case, the trench will go through plane (
111
) at a 45° angle. It has been found that this significantly reduces stress propagation/relief along the (
111
) direction and thereby reduces defects, especially at the STI corners.


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