Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-01-28
2003-09-02
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185080, C257S318000
Reexamination Certificate
active
06614684
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having electrically erasable and programmable nonvolatile memory elements. More particularly, the invention relates, for example, to techniques which are effective when applied to a semiconductor integrated circuit having a nonvolatile memory wherein two nonvolatile memory elements are used as a storage unit.
In recent years, as a memory device in which data or program-constituting data are stored, substantial public attention has been directed to a flash EEPROM (hereinbelow, termed “flash memory”), which is a nonvolatile storage device from/into which stored data/data to be stored are electrically erasable/programmable collectively in predetermined units. The flash memory has its memory cells configured of electrically erasable and programmable nonvolatile memory elements, and it is capable of erasing data or program-constituting data once written into the memory cells and rewriting (programming) new data or program-constituting data into the memory cells.
Therefore, for the purpose of, e.g., altering data, correcting the bugs of a program or updating a program after a flash memory or a macrocomputer having a built-in flash memory has been assembled into an application system, data or data constituting the program as stored in the flash memory can be altered, so that the term necessary for the development of the application system can be shortened, and so that the flexibility of the development of the program of the application system is enhanced.
On the other hand, in recent years, note has also been taken of a system semiconductor device (hereinbelow, also termed “system LSI”) wherein one system can be constructed of a single semiconductor integrated circuit device by forming on a single semiconductor substrate a central processing unit (hereinbelow, also termed “CPU”) as a data control device, a dynamic random access memory (hereinbelow, also termed “DRAM”) as a large-scale storage device, a static random access memory (hereinbelow, also termed “SRAM”) as a high-speed storage device or cache memory, and other functional circuits. Such a system LSI is effective for reducing the size of a printed circuit board or packaging circuit board, etc., and especially for reducing the size and lightening the weight of a portable telephone set, a portable data terminal, and similar portable equipment.
Incidentally, after the completion of the present invention, the inventors investigated into known examples from a viewpoint-A and a viewpoint-B, as stated below.
The viewpoint-A concerns the use of a polysilicon gate of single layer for forming the memory cell of a nonvolatile memory, while the viewpoint-B concerns the use of two memory cells in a differential fashion.
As a result, regarding the viewpoint-A, there have been found the official gazette of U.S. Pat. No. 5,440,159, the official gazette of U.S. Pat. No. 5,504,706, the official gazette of Japanese Pat. Application Laid-open No. 212471/1992(the official gazette of corresponding U.S. Pat. No. 5,457,335), and Oosaki et al., “A single Ploy EEPROM Cell Structure for Use in Standard CMOS Processes”, IEEE Journal of solid sate circuits”, VOL. 29, NO. 3, March 1994, pp 311-316.
On the other hand, regarding the viewpoint-B, there have been found the official gazettes of Japanese Patent Applications Laid-open No. 163797/1992, No. 311-316 263999/1989, No. 74392/1992, No. 127478/1992, No. 129091/1992 and No. 268180/1994, and the official gazette of U.S. Pat. No. 5,029,131.
By the way, the official gazette of Japanese Pat. Application Laid-open No. 212471/1992 discloses also a technique which utilizes an electrically programmable nonvolatile memory (EPROM) as a remedy circuit for a read only memory (ROM). Further, the official gazette contains the statement that the nonvolatile memory element of single-layer gate structure according to this invention can be utilized also as an electrically programmable and erasable nonvolatile memory element which executes programming with hot carriers and executes erasing with a tunneling current by applying a high voltage to a source or a drain, or which executes programming and erasing with tunneling currents.
SUMMARY OF THE INVENTION
The documents found by the investigation into the known examples have not disclosed at all the possibility that nonvolatile memory cells, each employing a single polysilicon layer may be utilized in a differential form, a discussion concerning the relationship between the initial threshold voltage of the memory cells (the threshold voltage in a thermal equilibrium state) and a word line potential in a data readout mode, in the case where the nonvolatile memory cells each employing the single polysilicon layer are utilized in the differential form, and so forth.
In addition, the following facts have been revealed by the inventors.
It has been found by the inventors that even a memory cell structure in the differential form has a first problem in that the occurring rate of readout faults ascribable to the deterioration of charge retention characteristics are greatly affected by the states of an initial threshold voltage under which no charge exists in a floating gate, threshold voltages in write and erase states, and a word line potential in a readout operation. Incidentally,
FIGS. 12 and 13
to be referred to below do not belong to known techniques, but they are drawings created by the inventors in order to facilitate the understanding of the present invention.
FIG. 12
shows the threshold voltage distribution of memory cells in the case where the initial threshold voltage (Vthi) is set comparatively high. By way of example, the initial threshold voltage (Vthi) is set higher than the average value between a low threshold voltage (VthL) as in the erase state and a high threshold voltage (VthH) as in the write state. The readout word line potential (Vread) is set in the medium range between the low threshold voltage (VthL) and the initial threshold voltage (Vthi). In the set state, the voltage difference between the initial threshold voltage (Vthi) and the high threshold voltage (VthH) under which electrons are accumulated in the floating gate is small. That is, the quantity of accumulated charges is small, and a retaining field strength which is applied to a tunnel oxide film in a retention state is low. As a result, the fall of the threshold voltage attributed to charge leakage from the floating gate is difficult to develop. On the other hand, an electric field in the direction of injecting electrons into the floating gate is applied to the tunnel oxide film of the memory cell of the low threshold voltage (VthL) by the word line voltage in the readout operation, so that the rise of the threshold voltage or a so-called “charge gain” develops. On this occasion, the undesirable rise of the threshold voltage mounts up to the initial threshold voltage (Vthi), so that when the threshold voltage has become higher than the readout word line potential (Vread), data is inverted so as to produce a readout fault. It has accordingly been revealed by the inventors that the characteristics as shown in
FIG. 12
are comparatively good at the data retention, but that they are less immune against the charge gain.
Contrariwise to the above,
FIG. 13
shows the threshold voltage distribution of memory cells in the case where the initial threshold voltage (Vthi) is set comparatively low. By way of example, the initial threshold voltage (Vthi) is set lower than the average value between the low threshold voltage (VthL) and the high threshold voltage (VthH). The readout word line potential (Vread) is set in the medium range between the low threshold voltage (VthL) and the initial threshold voltage (Vthi). In the set state, the voltage difference between the initial threshold voltage (Vthi) and the low threshold voltage (VthL) under which electrons are not accumulated in the floating gate is small, and the charge gain based on the word line voltage in the readout operation is difficult to occur. On th
Komori Kazuhiro
Kubota Katsuhiko
Okuyama Kousuke
Shukuri Shoji
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Phan Trong
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