Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2002-07-18
2003-07-15
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C324S760020, C324S763010, C361S789000
Reexamination Certificate
active
06591492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to multichip structures and, in particular, to chip interconnections in multichip structures.
2. Description of the Related Art
Semiconductor manufacturers continually strive to increase the packaging density of integrated circuit chips, which has led to the development of high density multichip modules, such as three-dimensional multichip structures. Multichip structures generally comprise a plurality of integrated circuit chips that are adhered together in a stack formation so as to reduce the amount of space that the chips occupy inside a system. It is generally understood that each chip in the stack typically has a plurality of conductive input/output (I/O) contacts that are exposed on a lateral surface of at least one edge of the chip. The exposed contacts provide a plurality of conductive I/O interconnects for wire bonding the device to external chips and circuitry.
As a result of the increased device density of VLSI (Very-Large-Scale Integration) and ULSI (Ultra-Large-Scale Integration) integrated circuitry, wiring conductive interconnects between input/output (I.O.) terminals of stacked integrated circuit chips has become increasingly more complex. The limitations brought about by the finite quantity of available space on the surface of a multichip structure and the levels of conductive traces that are required to wire complex integrated circuitry, such as microprocessors, memory modules, etc., has limited the interconnectivity between chips in multichip structures that require high-density conductive I/O interconnects.
One method of interconnecting chips within multichip structures is through the use of the generally known process of wire bonding. The I/O interconnection process of wire bonding often requires the formation of bondable wire bonding pads, which provide electrical contacts to I/O vias in the insulation layer of an integrated circuit chip. Unfortunately, bondable wire bonding pads may be relatively large. In addition, the available space on a substrate surface for surface mounting conductive I/O interconnects is limited by the finite dimensions of the device. As a result, the disadvantage to wire bonding as a method of I/O interconnection between integrated circuit chips is that the bonding pads consume a large amount of the available space on the integrated circuit chip surface. Therefore, the fabrication density is limited by the dimensions of the wire bonding pad and further by the finite dimensions of the integrated circuit chip surface. To further increase the fabrication density of integrated circuitry, a manufacturing process that reduces the need for wire bonding as a means for establishing a conductive link between I/O interconnects would be preferred.
In another aspect, integrated circuits chips within a multichip structure may be interconnected by a direct solderable C4 connection, but the I/O interconnection surfaces are usually limited to an opposed parallel positioning of the integrated circuit chips. An opposing parallel position refers to a chip configuration where the bonding elements are interposed between two parallel bonding plane surfaces of two opposing chips, which is similar to a sandwich configuration. Disadvantageously, the opposing parallel configuration reduces interconnection and mounting flexibility and can only be applied to parallel oriented chips in multichip structures, which is likely to reduce the available I/O interconnect density for chips that are not parallel and adjacent to one another.
Hence, it will be appreciated that there is a need for a method of increasing the interconnect density and interconnection flexibility between chips in multichip modules. There is also a need for a method of electrically connecting chips that are not positioned in an opposing parallel fashion. To this end, there is a particular need for a multichip structure that provides an increased interconnect density and flexibility between chips that are not positioned parallel to one another.
SUMMARY OF THE INVENTION
In one aspect, the preferred embodiments of the present invention disclose an integrated circuit module comprising a first semiconductor structure having a first surface defined by a first plane and a second semiconductor structure having a second surface defined by a second plane, wherein the second structure is positioned adjacent the first structure in a manner such that the second plane intersects the first plane. The module further comprises a first connecting member extending from the first surface of first structure. Preferably, the first connecting member has a first distal end that is electrically connected to the first surface and a second distal end extending from the first surface along a first axis.
Preferably, the module also comprises a second connecting member that is interposed between the second distal end of the first connecting member and the second surface of the second structure, wherein the second connecting member electrically interconnects the second distal end to the second surface and forms a bond therebetween along a second axis. Preferably, the second axis is not parallel to the first axis. In one embodiment, the first connecting member comprises a conductive pillar and the second connecting member comprises a solder ball. In another embodiment, both the first and second connecting members comprise conductive pillars and the conductive pillars may be joined together via solder.
In another aspect, the preferred embodiments of the present invention disclose a multichip module comprising a plurality of semiconductor chips stacked and secured together to form a base structure wherein the base structure has a first and a second lateral face, wherein each lateral face is comprised of a portion of each chip, wherein the first lateral face is adjacent to and substantially perpendicular to the second lateral face. The module further comprises a first exterior semiconductor chip mounted to the first lateral face of the base structure in a manner such that a first surface of the first exterior chip is positioned adjacent to the first lateral face and extends across at least a portion of the first lateral face. Preferably, the module also comprises a second exterior semiconductor chip mounted to the second lateral face of the base structure in a manner such that a first surface of the second exterior chip is positioned adjacent to the second lateral face and extends across at least a portion of the second lateral face. The first and second exterior chips are electrically connected via a connecting member. Preferably, the connecting member comprises a first distal end that is electrically connected to the first surface of the first exterior chip and a second distal end that is electrically connected to the first surface of the second exterior chip. In one embodiment, the connecting member comprises a conductive pillar. A solder ball is preferably interposed between the second distal end of the connecting member and the first surface of the second semiconductor chip. In another embodiment, the first distal end of the connecting member extends along a first axis and the second distal end extends along a second axis, wherein the first axis and the second axis are non-parallel.
In yet another aspect, the preferred embodiments of the present invention is directed to a method of forming electrical interconnections between two integrate circuit structures. The method comprises forming a first conductive contact on a first surface of a first semiconductor chip and a second conductive contact on a second surface of a second semiconductor chip. The method further comprises forming a connecting member on the first contact wherein a distal end of the connecting member extends from the first surface of the first semiconductor chip. The method further comprises positioning the chips in a manner such that the plane defining the first surface intersects with plane the defining the second surface. Furthermore, the method comprises affixing the dis
Arbes Carl J.
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
LandOfFree
Angled edge connections for multichip structures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Angled edge connections for multichip structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Angled edge connections for multichip structures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3009286