Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-04-07
2003-04-01
Shankar, Vijay (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S090000, C345S092000, C345S098000, C345S182000
Reexamination Certificate
active
06542139
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a matrix type display apparatus such as a liquid crystal display (hereinafter referred to as an LCD), and particularly to a technique for the enlarged display of a screen.
2. Description of the Related Art
FIG. 2
is a structural diagram of a conventional LCD.
This LCD displays image signals supplied from a personal computer or the like (referred to below as a PC) on a color screen having a size of 1024 pixels horizontally by 768 pixels vertically. This LCD comprises a control circuit
10
, a display signal circuit
20
, a scan signal circuit
30
, and a liquid crystal panel
40
.
Red, green, and blue color image signals formed from R, G, and B signals, clock signals CLK showing timings of a sampling of these R, G, and B signals, horizontal synchronizing signals HSYN, and vertical synchronizing signals VSYN are fed to the input side of the control circuit
10
from an unillustrated PC. On the basis of these signals, the control circuit
10
then generates start signals EI, clock signals CK, R, G, B data, and strobe signals STB and outputs these to the display signal circuit
20
. The control circuit
10
also has the function of generating start signals ST and clock signals CP and outputting these to the scan signal circuit
30
.
The display signal circuit
20
is provided with a 1024 stage shift register
21
which corresponds to the 1024 pixels in the horizontal direction, data latches
22
and
23
, and a display drive section
24
. The shift register
21
sequentially shifts and holds the start signals EI based on the clock signals CK and the held contents of each stage are fed to each stage of the data latch
22
as latch signals L
1
, L
2
, etc up to L
1024
. The data latch
22
holds the R, G, B data fed from the control circuit
10
based on the latch signals L
1
to L
1024
.
The data latch
23
stores the R, G, B data of the 1024 horizontal pixels held by the data latch
22
at the strobe signal STB timing. The display drive section
24
generates display voltages S
1
, S
2
etc up to S
3072
which correspond to R, G, B data of the 1024 pixels stored in the data latch
23
and outputs these display voltages.
The scan signal circuit
30
is provided with a 768 stage shift register
31
and scan drive section
32
for sequentially scanning and displaying the 768 pixels in the vertical direction in horizontal line units. The shift register
31
holds the start signals ST in the initial stage register as scan signals and then sequentially shifts these scan signals in accordance with the timing of the clock signals CP. The contents at each stage of the shift register
31
are fed to the scan drive section
32
and are output as scan voltages G
1
, G
2
, etc up to G
768
.
The liquid crystal panel
40
is provided with 768 X electrodes X
1
, X
2
, etc up to X
768
arranged at equal spacing in a line direction, and 1024 groups (note that each group is made up of 3 electrodes corresponding to R, G, and B) of Y electrodes Y
1
, Y
2
, etc up to Y
3072
arranged at equal spacing in a column direction. Color pixel display is performed in line units in accordance with display voltages S
1
to S
3072
applied respectively to the Y electrodes Y
1
to Y
3072
at locations where an X electrode Xj to which a scan voltage Gj (wherein j is a number from 1 to 768) is applied intersects with a Y electrode Y
1
to Y
3072
.
In this type of LCD, when R, G, B signals, clock signals CLK, horizontal synchronizing signals HSYN, and vertical synchronizing signals VSYN are supplied from a PC, horizontal cycle start signals EI and, thereafter, in synchronization with the clock signals CLK, R, G, B data is sequentially transmitted in single pixel units from the control circuit
10
to the display signal circuit
20
. In the shift register
21
, latch signals L
1
to L
1024
are generated in accordance with the clock signals CK. R, G, B data is further sequentially held in the data latch
22
in synchronization with the latch signals L
1
to L
1024
.
When the R, G, B data of the 1024 pixels of a single line is held in the data latch
22
, a strobe signal STB is output from the control circuit
10
. Accordingly, the R, G, B data of the single line in the data latch
22
is also stored in the data latch
23
. In the display drive section
24
, display voltages S
1
to S
3072
are generated based on the R, G, B data of the 1024 pixels stored in the data latch
23
and are output.
Moreover, start signals ST for each vertical cycle and clock signals CP for shifting the start signals ST and generating scan signals are output from the control circuit
10
to the scan signal circuit
30
. When the start signals ST are supplied, the output signal of the initial stage of the shift register
31
of the scan signal circuit
30
is set to a level “H” for designating display and output signals of subsequent stages are set to a level “L” for designating non-display. Output signals of each stage of the shift register
31
are then sequentially shifted one stage at a time towards the rear in synchronization with the clock signals CP which correspond to the horizontal cycle. The output signals of each stage of the shift register
31
are fed to the scan drive section
32
and scan voltages G
1
to G
768
are generated for each line in accordance with the display
on-display and output.
The display voltages S
1
to S
3072
which correspond to the R, G, B data of a single line output from the display drive section
24
are fed to the Y electrodes Y
1
to Y
3072
of the liquid crystal panel
40
. Moreover, the scan voltages G
1
to G
768
output from the scan drive section
32
are fed to the X electrodes X
1
to X
768
of the liquid crystal panel
40
. The timing of the strobe signals STB fed from the control circuit
10
to the display signal circuit
20
is substantially identical to the timing of the clock signals CP fed to the scan signal circuit
30
. Therefore, a single line which corresponds to the X electrode Xj driven by the scan voltage Gj output from the scan drive section
32
is displayed through the display voltages S
1
to S
3072
based on the R, G, B data for the single line stored in the data latch
23
. In addition, all other X electrodes other than the X electrode Xj are placed in a non-display state.
A screen is displayed by the X electrodes X
1
to X
768
being sequentially driven from top to bottom by the scan voltages G
1
to G
768
sequentially output from the scan drive section
32
.
However, this type of conventional LCD has the following problems.
For example, when an image signal supplied from a PC is for displaying on a 640 horizontal pixel by 480 vertical pixel screen, no pixel data exists for displaying at the right hand side and bottom of a liquid crystal panel
40
having 1024 horizontal pixels by 768 vertical pixels. Therefore, the problem has existed that the displayed screen is small and the display position is offset to the top left.
In order to solve this problem, attempts have been made to provide a processing device and frame memory corresponding to the resolution of the liquid crystal panel
40
in the LCD. Image signals fed from the PC are interpolated by this processing device and converted into image data for a 1024 horizontal pixel by 768 vertical pixel screen and displayed.
However, in this type of method, because a large amount of frame memory and a high speed processing device are necessary, the problem arises that costs are increased and the amount of power needed to run the processing device at high speed also increases.
SUMMARY OF THE INVENTION
The present invention solves the above problems in the conventional technology and provides a matrix type display apparatus such as an LCD which has a simple circuit structure and which is capable of enlarging the display of a screen.
In order to solve the above problems, the first aspect of the present invention is a matrix type display apparatus comprising: display means having M number of X electrodes (wherein M is a number greater than one)
Dharia Prabodh
Oki Electric Industry Co. Ltd.
Rabin & Berdo P.C.
Shankar Vijay
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