Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-05-21
2003-09-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S016000, C438S686000, C438S687000, C438S720000, C438S723000, C438S724000, C438S756000, C257S412000
Reexamination Certificate
active
06617176
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of copper interconnect material in conjunction with a diffusion barrier layer and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing copper diffusion from copper interconnect lines into the semiconductor substrate by increasing the effectiveness of a barrier material.
BACKGROUND ART
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-&mgr;m to 0.25-&mgr;m) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractory metals. Despite aluminum's (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower deposition temperatures. The copper (Cu) interconnect material may be deposited by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, electroless plating, and electrolytic plating.
However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon. These problems have instigated further research into the formulation of barrier materials for reducing electromigration in both Al and Cu interconnect lines. In response to electromigration concerns relating to the fabrication of semiconductor devices particularly having aluminum-copper alloy interconnect lines, the industry has been investigating the use of various barrier materials such as titanium-tungsten (TiW) and titanium nitride (TiN) layers as well as refractory metals such as titanum (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), their nitrides, and their carbides.
Although the foregoing materials are adequate for Al interconnects and Al—Cu alloy interconnects, they have not been entirely effective with respect to all-Cu interconnects. In particular, the effectiveness of a deposited thin conformal diffusion barrier layer, typically comprising refractory metals and their compounds, is difficult to determine. In the related art, a “line-to-line leakage” method is used in characterizing the effectiveness of barriers in preventing Cu diffusion; however, this method introduces interfaces that created undesirable rapid Cu diffusion pathways around the barrier layer and the dielectric layer rather than through the barrier layer and the dielectric layer, thereby short-circuiting the Cu diffusion, thereby resulting in the fabrication of devices having inferior barrier layers, and thereby imparting erroneous or misleading data. Further, the line-to-line leakage method only measures electrical current. Therefore, a need exists for a low cost and high throughput method of determining the copper penetration (i.e., diffusion) from the interconnect structure (or a metallized blanket layer) through the barrier layer, through an insulating layer, and into the semiconductor substrate for fabricating a semiconductor device for improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, and reducing copper diffusion, and a device thereby fabricated.
DISCLOSURE OF THE INVENTION
Accordingly, the present invention provides a method of determining the effectiveness of a deposited thin conformal diffusion barrier layer by forming a test specimen device and measuring the metal (e.g., Cu) penetration in the test specimen from a metallization layer through the barrier layer (e.g., refractory metals, their nitrides, their carbides, or their other compounds), through a thin insulating layer (e.g., SiO
2
), and into a semiconductor substrate (e.g., Si), under accelerated test conditions, for fabricating a production semiconductor device, wherein the interaction between the migrating metal ions and the semiconductor ions are detected/monitored, and wherein the detection/monitoring generally comprises: (1) stripping at least a portion of the insulating layer and the barrier layer; (2) examining the semiconductor substrate surface; and (3) adjusting the parameters for forming the barrier layer, thereby improving interconnect reliability, enhancing electromigration resistance, improving corrosion resistance, and reducing copper diffusion, and a test specimen device thereby formed.
By example only, the present invention involves a method comprising: (a) providing a semiconductor substrate for forming a test specimen; (b) forming a thin insulating dielectric layer on the semiconductor substrate; (c) forming a thin diffusion barrier layer on the thin insulating dielectric layer; (d) forming a metallized blanket layer on the diffusion barrier layer; (e) treating the blanket layer with at least one technique selected from a group consisting essentially of (1) heating the blanket layer and (2) applying a voltage bias to the blanket layer for instigating the metal penetration through the barrier layer and the insulating dielectric layer, thereby forming the test specimen; (f) measuring the metal penetration from the metallized blanket layer through the diffusion barrier layer, through the insulating dielectric layer, and into the semiconductor substrate of the test specimen by (1) stripping at least one portion of the insulating dielectric layer, at least one portion of the diffusion barrier layer, and at least one portion of the blanket layer, thereby exposing at least one portion of the semiconductor substrate surface; and (2) examining the exposed at least one portion of the semiconductor substrate surface for the metal penetration, thereby obtaining metal penetration measurement data corresponding to the at least one barrier layer formation parameter; (g) analyzing whether the metal penetration measurement data is within a given tolerance, as quantified, for example, by a diffusion mass flux rate, indicating an acceptable diffusion barrier performance (i.e., de minimis), and, if within the given tolerance, by proceeding to step (h), else adjusting the at least one barrier layer formation parameter and returning to step (a); and (h) fabricating at least one production device using the at least one barrier layer formation parameter, and a test specimen device thereby formed.
Advantages of the present invention include, but are limited to, fabricating a structure which better allows a quantitative determination of Cu penetration (from Cu diffusion) of through barriers and dielectrics (insulators) than does the related art. Unlike the related art “line-to-line leakage” method for characterizing the Cu diffusion, the present invention does not introduce rogue interfaces that create undesirable rapid Cu diffusion pathways around the barrier layer and the dielectric layer, but rather, the present invention measures the Cu diffusion propagating through the diffusion barrier layer and the insulating dielectric layer into the substrate, thereby preventing short-circuiting of the Cu diffusion, and thereby imparting accurate data. In contrast to the related art line-to-line leakage method which merely measures current along the rogue interfaces, the present invention allows for the calculation of mass flux diffusion rate. As such, the present invention provides better characterization of the diffusion properties of the presently claimed barrier layer, comprising advanced barrier materials, when used in conjunction with an insulating dielectric layer (e.g., SiO
2
as the dielectric material).
REFERENCES:
patent: 5332697 (1994-07-01), Smith et al.
patent: 5851912 (1998-12-01), Liaw et al.
patent: 5923999 (1999-07-01), Balasubra
Besser Paul R.
Mei-Chu Woo Christy
Sanchez, Jr. John E.
Wang Pin-Chin Connie
Advanced Micro Devices , Inc.
LaRiviere Grubman & Payne, LLP
Luk Olivia
Niebling John F.
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