Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2002-06-21
2003-05-20
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S730000, C257S690000, C257S700000, C257S737000, C257S779000, C257S734000
Reexamination Certificate
active
06566744
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits. In particular, the present invention relates to methods for forming integrated circuit packages.
2. Description of Related Art
Integrated circuit (IC) devices used in the semiconductor industry are frequently packaged prior to use in larger electronic systems, such as computers. The packaging is used to protect the small integrated circuit devices and to provide electrical connections to the contacts of the integrated circuits.
Ball grid array (BGA) packaging of integrated circuit devices is one method currently used to package integrated circuit devices in the semiconductor industry. BGA packaging has allowed integrated circuit packages to fit into smaller footprint regions to allow for a higher density of connections than earlier packaging methods, such as pin grid arrays. Typically, a ball grid array package is designed in a “fan-in” pattern in which solder ball connections are located directly above an integrated circuit and allow for electrical interconnection to the packaged integrated circuit device.
FIGS. 1A through 1D
illustrate cross-sectional views of one example of a method for forming a BGA integrated circuit package in the prior art.
In
FIG. 1A
, a conductive wiring layer
110
is applied to an entire integrated circuit wafer
112
. The integrated circuit wafer
112
typically includes a plurality of individual integrated circuit devices, and the wiring layer
110
forms interconnections to the individual integrated circuit devices on the wafer
112
.
In
FIG. 1B
, a dielectric layer
114
, such as a layer of SiO
2
is then formed over the wiring layer
110
.
In
FIG. 1C
, openings
116
are then formed in the dielectric layer
114
for receiving solder balls. Typically, the openings
116
are formed over the integrated circuit devices.
In
FIG. 1D
, the integrated circuit wafer
112
is then cut into individual packaged integrated circuit dies and solder balls
118
are deposited into the openings and reflowed to form the solder ball connections to the wiring layer
110
. The resulting integrated circuit packages have a fan-in arrangement of the solder ball connections over the integrated circuit device. Frequently, the integrated circuit packages are then attached to other components, such as a printed circuit board having a heat sink that provides heat dissipation for the packaged integrated circuit device.
FIG. 2
illustrates a top view of one example of a fan-in pattern of a BGA packaged integrated circuit device in the prior art. In the illustration, the integrated circuit package
210
has solder connections
212
located above the integrated circuit device
214
.
BRIEF SUMMARY OF THE INVENTION
The present invention includes methods for forming integrated circuit packages, such as BGA packaged integrated circuit packages, using fluidic self-assembly, and apparatuses formed thereby. According to one embodiment of the present invention, functional components, such as electronic integrated circuit components, having a wired side are suspended in a fluid and flowed over a substrate. The substrate has a top layer of a first dielectric and has recessed receptor regions for receiving the functional components. The functional components are deposited in the receptor regions using fluidic self-assembly such that the wired side is facing outward from the receptor region. A conductive layer, such as a wiring layer, is then formed on the first dielectric forming conductive interconnects to the wired side of the functional component. A second dielectric layer is then fabricated on top of the conductive layer. The second dielectric layer has openings for receiving conductive elements. Conductive elements, such as solder balls, are deposited into the openings in the second dielectric layer and contact the conductive layer. The substrate may then be separated into individual integrated circuit packages.
REFERENCES:
patent: 5188984 (1993-02-01), Nishiguchi
patent: 5545291 (1996-08-01), Smith et al.
patent: 6309912 (2001-10-01), Chiou et al.
Alien Technology Corporation
Talbott David L.
Zarneke David A.
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