Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2001-04-30
2003-01-14
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S123000, C257S666000, C257S783000
Reexamination Certificate
active
06506625
ABSTRACT:
1. Field of the Invention
This invention relates generally to semiconductor packaging, and specifically to an improved semiconductor package having a pair of stacked dice bonded to separate leadframes and encapsulated in a plastic body. This invention also relates to a method for fabricating the package, and to an electronic assembly fabricated using multiple packages.
2. Background of the Invention
A conventional plastic semiconductor package includes a semiconductor die attached to a segment of a leadframe, and encapsulated in a plastic body. One type of leadframe includes a mounting paddle that attaches to a backside of the die to support the die during encapsulation. The leadframe also includes lead fingers wire bonded to bond pads on the face of the die, then trimmed and formed into terminal leads for the package.
Another type of leadframe, known as a “lead-on-chip” (LOC) leadframe, includes lead fingers that attach directly to the face of the die to provide support during encapsulation, and the terminal leads for the package. Yet another type of leadframe comprises an organic polymer such as bismaleimide-triazine, epoxy or polyimide, reinforced with glass fibers.
In order to provide an increased circuit density and storage capability, a single semiconductor package can also include multiple semiconductor dice. For example, some semiconductor packages, known as “double die” packages, include two dice wired together with a common lead system. Other packages can include three, or sometimes more, semiconductor dice.
One consideration in fabricating multiple dice packages is heat transfer from the dice to the environment. With multiple dice contained in a package, at least twice the heat is generated during operation of the package. Some prior art multiple dice packages are not efficient in transferring heat generated by the dice. For example, packages that include organic lead frames, or lead frames with die mounting paddles, are generally not efficient at transferring and dissipating heat from the dice.
Another consideration in fabricating multiple dice packages is the efficiency of the fabrication process. Some packages require multiple encapsulation steps, which adds complexity to the fabrication process, and increases the expense of the packages. These fabrication processes can also require specialized equipment and materials.
In addition, multiple dice semiconductor packages having complex configurations may not be as reliable as conventional single die packages. In particular, the seal between the dice and package body can be compromised by the location and number of the parting lines between the dice and leadframe. Further, some multiple dice packages require complex wire bonding arrangements, such as relatively long length bond wires. These wire bonds can increase resistivity, generate parasitic signals, and adversely affect the reliability of the package.
The present invention is directed to a multiple dice semiconductor package having an efficient heat transfer path from the dice. In addition, the package has a simplified configuration, and can be fabricated using conventional equipment and materials.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved semiconductor package, a method for fabricating the package, and an electronic assembly fabricated using the package, are provided. The package includes first and second leadframe segments attached to one another, first and second semiconductor dice bonded to the leadframe segments in a stacked configuration, and a plastic body encapsulating the dice and leadframe segments.
In the illustrative embodiment, the package has the configuration of a thin small outline package (TSOP). In addition, the first leadframe segment has a lead-on-chip configuration and includes leadfingers attached to the first semiconductor die. The leadfingers on the first leadframe segment are wire bonded to bond pads on the first die, and include terminal portions that form terminal leads for the package. The second leadframe segment also has a lead-onchip configuration, and includes leadfingers attached to the second semiconductor die, and wire bonded to bond pads on the second semiconductor die. The leadfingers on the second leadframe segment are in electrical contact with the leadfingers on the first leadframe segment. Also, the leadfingers on the second leadframe segment are staggered with respect to the leadfingers on the first leadframe segment to permit space for bond wires.
The leadfingers, in addition to providing electrical paths for the package, also provide heat transfer paths for dissipating heat generated by the dice. The leadfingers also support the dice during the encapsulation process and rigidity the package.
The method for fabricating the package includes the steps of: providing a first leadframe having leadfingers configured to form terminal leads for the package; providing a second leadframe having leadfingers configured for electrical contact with the leadfingers on the first leadframe; attaching and wire bonding first semiconductor dice to the first leadframe; attaching and wire bonding second semiconductor dice to the second leadframe; attaching the leadframes to one another with the first and second semiconductor dice arranged in stacked pairs with their circuit sides facing one another; encapsulating the stacked pairs of semiconductor dice in plastic bodies; trimming and forming the first leadfingers to form terminal leads; trimming the second leadfingers; and then optionally plating the first and the second leadfingers to maintain electrical contact therebetween. The method of fabrication can be performed using conventional equipment adapted for use with lead-on-chip dice and leadframes.
In the illustrative embodiment the electronic assembly comprises a memory module comprising a substrate and multiple semiconductor packages mounted to the substrate.
REFERENCES:
patent: 5182632 (1993-01-01), Bechtel et al.
patent: 5227995 (1993-07-01), Klink et al.
patent: 5250941 (1993-10-01), Sloan et al.
patent: 5266912 (1993-11-01), Kledzik
patent: 5299092 (1994-03-01), Yaguchi et al.
patent: 5406124 (1995-04-01), Morita et al.
patent: 5437915 (1995-08-01), Nishimura et al.
patent: 5543658 (1996-08-01), Hosokawa et al.
patent: 5585600 (1996-12-01), Froebel et al.
patent: 5674785 (1997-10-01), Akram et al.
patent: 5677566 (1997-10-01), King et al.
patent: 5739585 (1998-04-01), Akram et al.
patent: 5763939 (1998-06-01), Yamashita
patent: 5811879 (1998-09-01), Akram
patent: 6252299 (2001-06-01), Masuda et al.
patent: 6303981 (2001-10-01), Moden
patent: 4-320362 (1992-11-01), None
patent: 4-320365 (1992-11-01), None
patent: 5-67726 (1993-03-01), None
patent: 5-782720 (1993-04-01), None
Fahmy Wael
Gratton Stephen A.
Micro)n Technology, Inc.
Toledo Fernando
LandOfFree
Semiconductor package having stacked dice and leadframes and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor package having stacked dice and leadframes and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor package having stacked dice and leadframes and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3006841