Semiconductor memory

Details Semiconductor memory Semiconductor memory

2002-01-17

2003-01-14

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185110, C365S230030

Reexamination Certificate

active

06507515

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the layout of a memory cell array in a semiconductor memory, and more particularly to a technology for reducing the chip size of a semiconductor memory.
2. Description of the Related Art
Semiconductor memories have sense amplifiers for amplifying data that is read out from memory cells to bit lines. In addition, nonvolatile semiconductor memories such as a flash memory have voltage generators for supplying a high voltage or a low voltage to source lines according to memory operations. U.S. patent application Ser. No. 5,293,350 has disclosed a technique in which a sense amplifier, a voltage generator, and the like are shared among a plurality of bit lines and the like, to reduce the chip size of the semiconductor memory.
FIGS. 1A and 1B
show the essential parts of a semiconductor memory of this type.
FIG. 1A
shows the circuit configuration and
FIG. 1B
shows a sectional structure of the area that is shown by the broken lines in FIG.
1
A.
A memory cell array
1
is provided with bit lines BL
0
and BL
1
, which are connected to its memory cells (not shown). The bit lines BL
0
and BL
1
are connected to a sense amplifier
3
(or a voltage generator etc.) through transistors
2
a
and
2
b
respectively and a common signal line CMN. The gates of the transistors
2
a
and
2
b
are connected to control lines
4
a
and
4
b
respectively. The control lines
4
a
and
4
b
are laid perpendicular to the bit lines BL
0
and BL
1
.
In this semiconductor memory, when the memory cell array is in a read operation, one of the control lines
4
a
and
4
b
is changed to a high level, turning ON either of the transistors
2
a
and
2
b
. It follows that one of the bit lines BL
0
and BL
1
is connected to the sense amplifier
3
through the common signal line CMN, whereby the data read out from a memory cell to the bit line BL
0
(or BL
1
) is amplified. That is, the sense amplifier
3
is shared between the bit lines BL
0
and BL
1
.
As shown in
FIG. 1B
, the transistor
2
a
is composed of diffusion layers (a source S and a drain D) which are formed in a semiconductor substrate SUB, and a control line
4
a
which is laid on the semiconductor substrate SUB via a gate insulator. The source S of the transistor
2
a
is connected to the common signal line CMN. The drain D of the transistor is connected to the bit line BL
0
. Since the broken-lined area of
FIG. 1A
allows no transistor that has the control line
4
b
as its gate, the source and the drain (diffusion layers) corresponding to the control line
4
b
are not formed in the semiconductor substrate SUB.
FIG. 2
shows an overview of the fabrication process for forming the source S and the drain D of the transistor
2
a.
The source S and the drain D are formed by implanting ions into the semiconductor substrate SUB with the gate of the transistor
2
a
(the control line
4
a
) as a mask. To form the transistor
2
a
, a photoresist
5
is initially applied to over the semiconductor substrate SUB (wafer) and then baked. Next, exposure is performed using a photomask
6
, followed by development, so that the photoresist
5
is processed into a shape corresponding to the photomask
6
as shown in FIG.
2
. Subsequently, as shown by the arrows in the diagram, phosphorus or other ions are implanted selectively to form the source S and the drain D of the transistor
2
a
. Here, no ion is implanted into the regions covered under the photoresist
5
(outside of the source S and the drain D of the transistor
2
a
). Thus, no transistor having the control line
4
b
as its gate is formed in the broken-lined area of FIG.
1
A.
As shown in
FIG. 1A
, the control lines
4
a
and
4
b
to be the gates of the transistors
2
a
and
2
b
are laid perpendicular to the bit lines BL
0
and BL
1
. The transistors
2
a
and
2
b
are formed by implanting ions with these control lines
4
a
and
4
b
as masks. This requires that regions undesired of transistor formation (for example, the regions adjacent to the control line
4
b
within the broken-lined area of
FIG. 1A
) must be masked with the photoresist
6
. In other words, to selectively connect the bit lines BL
0
and BL
1
to the sense amplifier
3
and the like, the photoresist
6
needs to be opened for each of the transistors
2
a
and
2
b
corresponding to the bit lines BL
0
and BL
1
, respectively.
The openings in the photoresist
6
must be made with predetermined margins from the regions to form transistors and those not to form transistors. Owing to these margins, there has been a problem of an increased layout area when the wiring spacing between the control lines
4
a
and
4
b
needs to be extended beyond the formable minimum process size. Since the increased layout area grows the chip size of the semiconductor memory, there has been a problem of a rise in product costs. The memory cell array and its peripheral regions (sense-amplifier regions etc.) contain a number of identical circuits arranged repeatedly. On this account, an increase in the layout area of these regions has a significant impact on the product costs of the semiconductor memory.
SUMMARY OF THE INVENTION
It is an object of the present invention to improve the integration level of a memory cell array and its periphery to reduce the chip size of a semiconductor memory.
According to one of the aspects of the present invention, a semiconductor memory has a plurality of memory cell rows, an input/output circuit for inputting/outputting data to/from the memory cell rows, and a plurality of first transistor rows arranged for each of the memory cell rows. The memory cell rows include a plurality of memory cells connected in series. For example, the memory cells are nonvolatile memory cells each having a control gate and a floating gate, and the memory cell rows are configured as a NAND type.
The first transistor rows have a plurality of transistors connected in series. For example, the memory cell rows are connected to the first transistor rows through local bit lines, respectively. The first transistor rows are connected to the input/output circuit through a global bit line, which is common to these transistor rows.
In each first transistor rows, a switching transistor operates as a switch while a short transistor(s) each having a source and a drain shorted to each other function(s) as wiring. When performing a read/write operation from/to the memory cells, any of the switches (transistors) among the plurality of first transistor rows turns on to selectively connect any of the memory cell rows to the input/output circuit. That is, the input/output circuit is shared among the plurality of memory cell rows.
The first transistor rows are provided with the plurality of transistors in advance regardless of whether or not to use the transistors as switches. Since there is no need to selectively form only such a transistor that is to be operated as a switch, there is no need to form ion-implanted regions for making a source and a drain per transistor. As a result, the pattern shape of the photomask corresponding to the ion-implanted regions (the layout rule of the diffusion layer regions) need not be taken account of when arranging the spacing between the transistors of the first transistor rows (the wiring spacing of the gate material). Since the transistors can be arranged closely, the layout area of the first transistor rows can be reduced. This allows a reduction in the chip size of the semiconductor memory. The present invention offers a high effect when applied to nonvolatile semiconductor memories of NAND type which feature high integration.
According to another aspect of the present invention, the semiconductor memory is provided with a plurality of the memory cell rows corresponding to each of the first transistor rows. These memory cell rows are respectively connected to a corresponding transistor row of the first transistor rows through selecting transistors in each of the memory cell rows. Since any of the memory cell rows are select

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