Liquid crystal cells – elements and systems – Nominal manufacturing methods or post manufacturing... – Defect correction or compensation
Reexamination Certificate
2001-02-15
2003-07-08
Kim, Robert H. (Department: 2871)
Liquid crystal cells, elements and systems
Nominal manufacturing methods or post manufacturing...
Defect correction or compensation
C349S054000, C349S122000, C349S138000
Reexamination Certificate
active
06590630
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a thin film transistor liquid crystal device and a method of fabricating the same. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for easily detecting a short line defect, thereby increasing yield in fabricating a liquid crystal display.
2. Discussion of the Related Art
A liquid crystal display (LCD) has been widely used in office automation equipment and video units because it has advantages in size and power consumption. Such an LCD typically utilizes an optical anisotropy of a liquid crystal (LC). The LC has thin and long shape molecules, which causes an orientation alignment of the LC molecules. Therefore, an alignment direction of the LC molecules are be controlled by applying electric fields to the LC molecules. When the alignment direction of the LC molecules are properly adjusted, the LC is aligned and light is reflected along the alignment direction of the LC molecules in displaying image data.
An active matrix (AM) LCD having a plurality of thin film transistors (TFTs) and pixel electrodes arranged in the shape of an array matrix draws most attention because of its high resolution and superiority in displaying moving pictures. The active matrix type liquid crystal display device, employing a TFT as a switching device, is formed on an array substrate having a matrix array of TFTs and pixel electrodes, and an opposing substrate arranged opposing the TFT substrate, with a liquid crystal material interposed therein. The opposing substrate includes a light-shielding film (so called a black matrix), a color filter and a common electrodes.
Now, referring to the attached drawings, a conventional back-channel-etching type structure of an array substrate of the liquid crystal display device manufactured by a conventional method is explained in detail. As shown in
FIG. 1
, a liquid crystal display
20
includes an array substrate
2
, a color filter substrate
4
facing into the array substrate
2
, a liquid crystal
10
interposed between the array and color filter substrates
2
and
4
, and a sealant
6
formed at the periphery of the gap between the two substrates
2
and
4
. The sealant
6
prevents the liquid crystal
10
from leaking out of the liquid crystal display device
20
.
The array substrate
2
includes a substrate
1
, a thin film transistor “S” as a switching element for changing an orientation of the liquid crystal
10
, and a pixel electrode
14
as a first electrode for applying electric fields to the liquid crystal
10
. The color filter substrate
4
includes another substrate
1
, a color filter
8
for displaying colors, and a common electrode
12
as a second electrode for applying electric fields to the liquid crystal
10
. A pixel region “P” includes the pixel electrode
14
and serves as a display area for displaying images.
Referring to
FIG. 2
, a detailed description of the structure and operation of the array substrate
2
will be followed. On the substrate
1
, a gate line
22
is transversely formed with a data line
24
arranged perpendicular thereto, and a pixel electrode
14
is formed on the area defined by the gate and data lines
22
and
24
. Near the cross point between the gate and data lines
22
and
24
, a portion of the gate line
22
is used as a gate electrode
26
. Further, near the cross point between the gate and data lines
22
and
24
, a source electrode
28
is protruded from the data line
24
spaced apart from the source electrode
28
and a drain electrode
30
is formed. The TFT “S” includes the gate electrode
26
, the source electrode
28
, and the drain electrode
30
as well as an active layer
55
, which usually serves as the most important element to switch the liquid crystal layer (reference numeral
10
of FIG.
1
). Since it is easy to form an amorphous silicon layer at a relatively low temperature such as below 350° C., amorphous silicon is conventionally used for the active layer
55
.
While not shown in
FIG. 2
, data pads and gate pads are respectively formed at each end of the data lines and gate lines. The data and gate pads (not shown) electrically connect the TFT “S” and the pixel electrode
14
with corresponding external driving circuits (not shown), respectively. The TFT “S” serves as a switching device to apply signals for the pixel electrode
14
.
Still referring to
FIG. 2
, a drain contact hole
34
is formed over the drain electrode
30
. The pixel electrode
14
(shown in
FIG. 1
) electrically contacts the drain electrode
30
through the drain contact hole
34
. A capacitor electrode
21
is integrally formed with the gate line
22
, and overlaps the pixel electrode
14
to form a storage capacitor Cst. The storage capacitor Cst serves to store electric charges.
As explained previously, the TFT “S” including the gate, source, and drain electrodes
26
,
28
and
30
acts as a switch for applying electric fields to the liquid crystal
10
(shown in FIG.
1
). That is a say, in operation, if only signals are applied to the gate electrode
26
of the TFT “S”, the electric fields are applied to the pixel electrode
14
. The signals applied to the TFT “S” are transmitted from an outer circuit (not shown), which is electrically connected with the data and gate pads (not shown).
A fabricating process of the above-mentioned array substrate requires repeated steps of depositing and patterning of various layers. The patterning step adopts a photolithography mask step including light exposing with a mask. Since one cycle of the photolithography step is facilitated with one mask, the number of masks used in the fabrication process is a critical factor in determining the number of patterning steps. As the fabricating process for the array substrate becomes simpler, errors may decrease. The fabricating process for the array substrate is set out according to design specifications for the array substrate or materials used for the various layers in the array substrate. For example, in case of fabricating a large-scaled (12 inches or larger) LCD, a specific resistance of a material for the gate lines serves as a critical factor in determining the quality of the LCD. Therefore, a highly conductive metal such as aluminum (Al) or aluminum alloys are usually used for the large scaled LCD device.
Referring now to
FIGS. 3A
to
3
E, a fabrication method and a more detailed description of the structure of the TFT and the storage capacitor will be discussed as follows. For the TFT, an inverted staggered type is widely employed due to its advantages of a simple structure and a superior quality. The inverted staggered tube TFT is divided into a back-channel-etch type and an etching-stopper type according to a method of forming a channel in the TFT. The back-channel-etch type has a simpler structure.
FIGS. 3A
to
3
E refer to the back-channel-etch type TFT.
At first, a glass substrate
1
is cleaned to remove particles or contaminants on the surface of the substrate
1
. Then, as shown in
FIG. 3A
, a first metal layer is deposited on the substrate
1
and patterned by lithography to form the gate electrode
26
, the gate line (reference numeral
22
of FIG.
2
), and the capacitor electrode
21
. Aluminum is widely used for the gate electrode
26
to decrease a RC delay. However, a pure aluminum is chemically weak and may involve an occurrence of a hillock in a high-temperature process. Therefore, aluminum alloys or a layered aluminum is used for the gate electrode instead of a pure aluminum.
Next, as shown in
FIG. 3B
, a gate insulating layer
5
C is formed on the substrate
1
to cover the first patterned metal layer including the gate electrode
26
and the capacitor electrode
21
. Thereafter, an amorphous silicon layer
52
(a-Si:H) and a doped amorphous silicon layer
54
(n+a-Si:H) are sequentially formed on the gate insulating layer
50
. The silicon layers
52
and
54
are patterned to form the active l
Kim Robert H.
LG.Philips LCD Co. , Ltd.
Morgan & Lewis & Bockius, LLP
Schechter Andrew
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