Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-04-18
2003-09-09
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
Reexamination Certificate
active
06617665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the forming of inductive windings (inductances) on an integrated circuit chip. More specifically, the present invention relates to the forming of inductances intended to receive high-frequency currents, such as, for example, high-frequency antennas of mobile phones or filters.
2. Discussion of the Related Art
FIGS. 1A
to
1
D illustrate, in a simplified partial cross-section view, the forming of an inductance according to a conventionally-implemented step sequence. More specifically,
FIGS. 1A
to
1
D are cross-section views along the width of an inductance spiral.
As illustrated in
FIG. 1A
, a trench is first opened in an insulating layer
10
according to the inductance pattern. A layer of a conductive material
11
is then deposited to completely fill the previously-opened trench.
At the next steps, illustrated in
FIG. 1B
, layer
11
is etched to be removed from the upper surface of insulating layer
10
. For this purpose, a chem-mech polishing (CMP) is performed. A first horizontal conductive level
12
has thus been formed. As discussed previously,
FIG. 1
is a cross-section view along the width of a spiral of the inductance. First level
12
extends over the entire inductance pattern, and is common to all its spirals. Then, an insulating layer
13
is deposited. Layer
13
is deposited so that its upper surface is substantially planar.
As illustrated in
FIG. 1C
, distinct openings are formed in layer
13
to partially expose different portions of the upper surface of first level
12
. Then, these openings are filled with a conductive material
14
, preferably identical to conductive material
11
forming first level
12
.
After deposition over the entire structure of material
14
, a chem-mech polishing is performed to remove material
14
from the upper surface of insulating layer
13
.
Parallel conductive vias
16
in contact with first level
12
are thus individualized, as illustrated in FIG.
1
D. Then, an insulating layer
17
is deposited so that its upper surface is substantially planar. A second horizontal conductive level
18
is then formed above first level
12
and interconnects all vias
16
. Second level
18
is formed by opening a trench according to an appropriate pattern in insulating layer
17
, then by depositing a conductive material, preferably identical to conductive material
11
, and finally performing a chem-mech polishing (CMP) to only maintain in place the copper in the previously-formed trench.
An inductance with spirals including first and second horizontal conductive levels
12
and
18
interconnected by vias
16
is thus formed. Interconnection lines or vias may be formed in insulating layers
10
,
13
, and/or
17
simultaneously with first level
12
, with vias
16
and/or with second level
18
.
In applications of telecommunication type, inductances are conversely deposited above integrated circuits, no other conductive element being formed in insulating layers
10
,
13
, and
17
. Such inductances, intended to be used as antennas in high-frequency devices, must exhibit a maximum quality factor Q and be able to operate at an optimal resonance frequency and/or in the widest possible frequency band.
Increasing factor Q leads to reducing the resistance of the inductance. For this purpose, it has already been provided to use as a conductive material forming levels
12
and
18
and vias
16
lightly resistive materials such as copper or copper-based alloys. To further reduce the resistivity, it has then been provided to increase the surface area of levels
12
and
18
and of vias
16
. This increase being impossible in the thickness of successive layers
10
,
13
,
17
determined by other standard constraints of microelectronics methods, the widest possible levels
12
and
18
have been formed in layers
10
and
17
, correspondingly increasing the number of vias
16
in layer
13
. However, such a width increase of levels
12
and
18
is limited by the chem-mech polishing implemented to individualize the spirals in each layer. Indeed, in a CMP of a relatively wide copper surface, a power consumption of this surface, that is, the forming of a hole with a poorly defined depth and extent, can be observed. The real resistance of the line conducting a given current is then increased and quality factor Q is decreased. This decrease in quality factor Q is uncontrolled. Further, if the surface area is too large, this deformation may occur to the extent of tearing up the conductive line. This results in a spiral breakage.
Another disadvantage of a widening of levels
12
and
18
is the negative impact on the resulting electric performances. Indeed, when the inductance so formed conducts a given current, said current generates a magnetic field which itself gives rise to an inverse current, called an eddy current. This inverse current corresponds to an increase in the real resistance. Now, this eddy current is proportional to the spiral width, and not to its thickness or its length. Increasing the spiral width thus results in increasing the real resistance and correspondingly decreasing quality factor Q.
Further, when a high-frequency electric current is attempted to be directed through a conductor, the current tends to only flow at the periphery of the conductive volume (skin effect). In other words, for high-frequency currents, instead of taking advantage of the entire conductive surface, the current limits to a small peripheral surface. The current being of relatively high frequency, everything occurs as if the current would flow in a conductor of high real resistance. The quality factor is further lowered. Accordingly, the frequency range, that is, the maximum frequency which can be reached by a current flowing through such an inductance, is limited.
Currently, given the various previously-discussed problems, inductances stand currents having a frequency of at most 50 Hz.
At the same time, the desire to transmit a higher and higher number of data, and the frequency range congestion leads to searching communication systems adapted to operating at the highest possible frequencies with optimized quality factors.
SUMMARY OF THE INVENTION
The present invention accordingly aims at providing an inductance formed in an integrated circuit chip, having a perfectly controlled quality factor.
The present invention aims at providing such an inductance having a relatively high frequency band.
The present invention also aims at providing such an inductance, the manufacturing of which inscribes in the step sequence currently implemented in the manufacturing of the metallizations of an integrated circuit.
To achieve these and other objects, the present invention provides an inductance formed in an integrated circuit chip, formed of a plurality of parallel conductive lines, of optimized width, each conductive line being formed in the thickness of at least one insulating layer, these lines being interconnected by at least one perpendicular conductive segment.
According to an embodiment of the present invention, the optimized width is equal to twice the skin thickness corresponding to the maximum frequency of a high-frequency current running through said inductance.
According to an embodiment of the present invention, the conductive lines are formed in three insulating layers and the conductive segments are formed in at least one of the three insulating layers.
The present invention also includes a method for forming an inductance in monolithic form, including the step of forming in at least one insulating layer, along the inductance pattern, a plurality of parallel conductive lines and segments perpendicular to said lines and intercepting all of them.
According to an embodiment of the present invention, the conductive lines have a width equal to twice the skin thickness corresponding to the maximum frequency of a high-frequency current intended to be conducted by the inductance.
According to an embodiment of the present invention, any step of forming and/
Arnal Vincent
Farcy Alexis
Torres Joaquim
McClellan William R.
Morris James H.
STMicroelectronics S.A.
Tsai Jey
Wolf Greenfield & Sacks P.C.
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