Data processing: measuring – calibrating – or testing – Measurement system – Temperature measuring system
Reexamination Certificate
2002-07-12
2003-03-11
Shah, Kamini (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Temperature measuring system
Reexamination Certificate
active
06532431
ABSTRACT:
FIELD
This invention relates to the field of integrated circuit fabrication. More particularly, this invention relates to testing integrated circuits.
BACKGROUND
There is continual pressure for integrated circuits to be increasingly faster and increasingly more powerful. Both of these objectives tend to be influenced by the size of the integrated circuits. By fabricating smaller integrated circuits, electrical pathways are shorter and more devices are formed within a given space, which tends to result in a faster, more powerful integrated circuit. Thus, feature sizes of integrated circuits tend to be continually reduced. Current processing techniques are entering what is commonly called the very deep sub micron range, in which minimum feature sizes range from about one hundred nanometers to about one hundred and eighty nanometers or so.
At such small feature sizes, the integrated circuits perform differently than they do at larger feature sizes. Thus, processing methods and testing methods that were valid, reliable, and cost effective at larger feature sizes may no longer be so at the smaller feature sizes. For example, at the smaller feature sizes, parameters such as intrinsic leakage tends to increase to a level where traditional test limits cannot be reliably applied. More specifically, tests such as IDDq, minimum VDD (VDDmin), maximum VDD (VDDmax), and frequency are generally anticipated to have an end of utile life at very small feature sizes. The screening of very deep sub micron defects and subtle defects such as resistive paths and timing defects are therefore very difficult to screen and more likely to become test escapes and may cause failures in the end application.
Currently used procedures for IDDq testing, for example, include sensing IDDq at a first temperature and comparing the first sensed values to a first set of criteria, and then sensing IDDq at a second temperature and comparing the second sensed values to a second set of criteria. Devices with values that violate either of the two sets of criteria are flagged, such as for scrap. However, this old method does not provide a solution for monitoring the defects that show significantly different temperature characteristics from so-called good devices. This aspect becomes more important for small featured devices as the current levels of the good devices increase into the milliampere or ampere range.
What is needed, therefore, is a method of testing small featured integrated circuits, such as integrated circuits in the very deep sub micron range, whereby parameter tests such as IDDq, VDDmin, VDDmax, and frequency provide valid results.
SUMMARY
The above and other needs are met by a method of testing an integrated circuit. The thermal energy of the integrated circuit to adjusted to a first temperature, and a first set of electrical characteristics of the integrated circuit are sensed at the first temperature. The first set of electrical characteristics are recorded in association with an identifier for the integrated circuit. The thermal energy of the integrated circuit is adjusted to a second temperature, and a second set of electrical characteristics of the integrated circuit are sensed at the second temperature. The electrical characteristics of the second set correspond to the electrical characteristics of the first set. The second set of electrical characteristics are also recorded in association with the identifier for the integrated circuit. Ratios are created between the corresponding recorded electrical characteristics of the first set and the recorded electrical characteristics of the second set for the integrated circuit, as determined by the identifier for the integrated circuit. A first categorization is applied to the integrated circuit if the ratios are within a first limit range, and a second categorization is applied to the integrated circuit if the ratios are not within the first limit range.
In this manner, the potentially defective integrated circuits that have significantly different ratios than the intrinsically good integrated circuits are identified in a production worthy method of screening. The method can be used on tester or as a statistical post process. This provides a method of screening integrated circuits even when the intrinsic leakage of the technology increases to a level at which traditional test limits, such as those for IDDq, VDDmin, VDDmax, and frequency cannot be applied.
In various preferred embodiments of the invention, further processing of the integrated circuit is selectively accomplished when the first categorization is applied to the integrated circuit, and processing of the integrated circuit is selectively stopped when the second categorization is applied to the integrated circuit.
In one embodiment the first temperature is lower than the second temperature, and the thermal energy of the integrated circuit is adjusted to a first temperature by either cooling the integrated circuit or heating the integrated circuit. Alternately, the first temperature is higher than the second temperature, and the thermal energy of the integrated circuit is adjusted to the second temperature by either cooling the integrated circuit or heating the integrated circuit.
Most preferably, sensing the first set of electrical characteristics of the integrated circuit at the first temperature and sensing the second set of electrical characteristics of the integrated circuit at the second temperature includes sensing at least one of IDDq, VDDmin, VDDmax, and frequency. In a most preferred embodiment, the first limit range is a three sigma limit around an arithmetic mean of the ratios.
In a preferred embodiment, sensing the first set of electrical characteristics of the integrated circuit at the first temperature is accomplished at wafer sort and sensing the second set of electrical characteristics of the integrated circuit at the second temperature is accomplished at final test. The first set and second set of electrical characteristics are preferably recorded in association with the identifier for the integrated circuit by saving the characteristics on computer writable and readable media.
REFERENCES:
patent: 5732209 (1998-03-01), Vigil et al.
patent: 5926027 (1999-07-01), Bumb et al.
patent: 6032268 (2000-02-01), Swoboda et al.
patent: 6162652 (2000-12-01), Dass et al.
patent: 6400173 (2002-06-01), Shimizu et al.
LSI Logic Corporation
Luedeka Neely & Graham PC
Shah Kamini
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