Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-02-07
2003-07-15
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S324000, C327S309000, C361S091700
Reexamination Certificate
active
06593794
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to electrostatic discharge protection for electronic circuits; more particularly, the invention is directed to electrostatic discharge protection for high-speed integrated circuits, i.e., integrated circuits handling signals having frequencies higher than electrostatic discharge transients.
2. Background of the Related Art
Advances in integrated circuit development continue to increase the density of circuit components that can be fabricated in an integrated circuit (IC) chip. In conjunction with this advance in miniaturization, critical dimensions of the IC such as minimum conductor-to-conductor spacing and layer thicknesses also have been reduced. In particular, insulating layers within the IC structure have become thinner, making ICs more susceptible to electrostatic discharge (ESD) pulses. The pulses are passed to the IC circuit from an input or output pin, and if not properly diverted could deliver a brief but highly destructive charge to the IC circuitry.
As is known in the art, ESD protection circuits can be fabricated in the ICs.
Typically, these circuits are disposed on the input and output pads of the ICs and pass normal input signals therethrough while diverting ESD pulses as shown in FIG.
1
. Here, an input or output bonding pad
10
of an IC is connected to an internal circuit
20
to be protected from ESD pulses via a conductor
30
(as used herein, “input/output bonding pad” denotes that the bonding pad may be used for receiving input signals, providing output signals, or both). Desired signals pass in one or both directions between the bonding pad
10
and the internal circuit
20
. Were the IC to have no ESD protection, an ESD pulse appearing at the bonding pad
10
would be conducted via conductor
30
to the internal circuit
20
, possibly damaging or destroying it by, e.g., shorting through one or more oxide layers in the IC. However, ESD protection circuit
40
is activated by the relatively high voltage levels (relative to the IC's internal supply voltage) of the ESD pulses and establishes a low-resistance conductive path between conductor
30
and the ground connection to shunt the ESD pulse away from the internal circuit
20
.
As one of ordinary skill in the art will recognize, in practice most protected circuits are equipped with not only one ESD protection circuit
40
between conductor
30
and system ground or V
SS
, but also with another between conductor
30
and a positive source of potential, such as V
DD
. This allows the ESD pulse to be discharged either through the V
SS
or V
DD
pad. However,
FIG. 1
shows only a single ESD device
40
in the interests of simplicity and ease of explanation.
A typical ESD device
40
as described above is shown in FIG.
2
. Here, an N-channel MOS transistor
50
is connected between conductor
30
and V
SS
. A resistor
70
is connected between the gate of transistor
50
and V
SS
. A capacitor
60
(which may be a parasitic capacitance of transistor
50
or a separate component) is connected between conductor
30
and the gate of transistor
50
. Transistor
50
has a parasitic bipolar mode of operation designated by transistor
50
′. The transistor
50
is very wide with a short channel length, e.g., 300 &mgr;m wide by 0.5 &mgr;m long, to be capable of efficiently shunting the current due to an ESD event (the current due to an ESD event is proportional to the amount of static charge deposited on the IC, and the current is typically between a few tenths of an ampere and a few amperes). By effectively choosing the values of capacitor
60
and resistor
70
, the gate of transistor
50
will rise to a voltage of about 1 volt when an ESD event occurs and the voltage on node A rises above a trigger voltage of about 4.0 to 7.5 volts, depending on the IC fabrication technology in use. When the transistor
50
is turned on by such an ESD event, bipolar conduction through transistor
50
′ will begin and continue until the voltage on node A falls below the trigger voltage level.
While this arrangement is workable in some applications, the ESD device
40
typically presents a relatively large capacitive loading
40
′ (on the order of a few picofarads) to the bonding pad
10
and internal circuit
20
. This limits the maximum frequency of desired signals which can be exchanged between bonding pad
10
and internal circuit
20
.
Prior art attempts at ameliorating this effect have reduced the size of the ESD protection transistor to lessen the capacitive loading to the IC; however, this necessarily reduces the level of protection afforded by the ESD protection circuit. As the frequency of signals processed by the IC increases, the ESD protection transistor becomes too small to be effective.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the above shortcomings of the prior art.
It is another object of the present invention to provide a circuit for ESD protection which minimizes the capacitive loading on the inputs and outputs of the circuit which it protects.
It is a further object of the present invention to provide a circuit for ESD protection which is particularly useful with circuits processing high frequency signals.
It is still another object of the present invention to provide a circuit for ESD protection which provides effective ESD protection in high-frequency environments.
It is yet another object of the present invention to provide a circuit for ESD protection which provides effective ESD protection for circuits processing signals at frequencies above those of ESD pulses.
The above objects are achieved according to a first aspect of the present invention by providing an ESD protection circuit which uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while isolating its capacitive load on the main circuit when presented with desired signals which are higher in frequency than ESD pulses. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires.
REFERENCES:
patent: 4315229 (1982-02-01), Greaves et al.
patent: 4383229 (1983-05-01), Jones
patent: 4806999 (1989-02-01), Strauss
patent: 4935839 (1990-06-01), Lockwood
patent: 4958255 (1990-09-01), Pritchard
patent: 5293298 (1994-03-01), Foglia
patent: 5357397 (1994-10-01), Leary
patent: 5469107 (1995-11-01), Kohno
patent: 5576680 (1996-11-01), Ling
patent: 5584870 (1996-12-01), Single et al.
patent: 5706163 (1998-01-01), Kalb et al.
patent: 5712753 (1998-01-01), Yeh et al.
patent: 5715127 (1998-02-01), Yu
patent: 5896113 (1999-04-01), O'Neill
patent: 5901022 (1999-05-01), Ker
patent: 5917220 (1999-06-01), Waggoner
patent: 5969929 (1999-10-01), Kleveland et al.
patent: 6005756 (1999-12-01), Lane
patent: 6014066 (2000-01-01), Harberts et al.
patent: 6034400 (2000-03-01), Waggoner et al.
patent: 6057714 (2000-05-01), Andrys et al.
patent: 6459343 (2002-10-01), Miller
patent: 0478890 (1992-04-01), None
patent: 0741413 (1996-06-01), None
patent: 0851555 (1998-07-01), None
patent: 11067486 (1999-03-01), None
J. Craninckx, et al, “A 1.8-GHz CMOS Low-Phase-Noise Voltage-Controlled Oscillator with Prescaler”, IEEE Journal of Solid State Circuits, vol. 30, No., 12, Dec. 1995, pp. 1474-1482.
Chik P. Yue, “On-Chip Spiral Inductors For Silicon-Based Radio-Frequency Integrated Circuits”, Technical Report No. ICL 98-087, Department of Electrical Engineering, Stanford University, Jul. 1998.
McFarland William John
Su David Kuochieh
Wong Siu-Weng Simon
Yue Chik Patrick
Atheros Communications
Cunningham Terry D.
Rosenberg , Klein & Lee
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