Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2000-07-17
2003-04-22
Shalwala, Bipin (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S037000, C345S041000, C345S060000, C345S690000
Reexamination Certificate
active
06552701
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a display method for a plasma display device for displaying gradation by a sub-field technique. More particularly, it relates to a display method for a plasma display device reducing a dynamic-image pseudo contour in a large-area flicker that occurs when a television signal of a relatively low vertical synchronizing frequency or the like is displayed.
2. Description of the Related Art
It is a common practice to use the sub-field technique to display gradation in a display device, which can provide only binary display in principle, such as a plasma display device that employs a memory effect for display. The sub-field technique can be applied to a display device that can provide quick response such as a plasma display device. This technique quantizes a video signal and displays the resulting one-field data by time-sharing for each gradation bit.
Specifically, one field is divided into a kind of group of fragmented fields or a plurality of so-called sub-fields, each of which is weighted by the number of times of light emissions corresponding to each gradation bit. Then, the sub-field technique or a time-sharing technique is used to reproduce images in sequence to accumulate the images over one field by the integral effect of vision, so that natural gradation images are expressed.
For example, to realize a 256-level gradation display, the sub-field technique quantizes (converts analog to digital) in general an input analog video signal to brightness signals of 8 bits corresponding to gradation brightness data, each brightness of which differs by two times.
Then, the quantized video signal data is accumulated in a frame buffer memory.
Let the most significant bit MSB having the highest brightness be designated by B
1
, a bit having the second highest brightness by B
2
, and other bits by B
3
, B
4
, B
5
, B
6
, B
7
, and B
8
, respectively. The brightness ratio among the bits corresponds to 128:64:32:16:8:4:2:1. These bits are selected by each pixel, so that 256 levels of gradation can be realized in total, which correspond to brightness levels from 0 to 255.
FIG. 1
is a schematic diagram showing a prior-art display method for an AC color plasma display device. The method shown in
FIG. 1
employs a sub-field technique in accordance with scan/sustain separate driving. As shown in
FIG. 1
, one field is divided into 8 sub-fields, or sub-fields SF
1
to SF
8
, each of which has a scan period and a sustaining discharge period. During the scan period of the sub-field SF
1
, display data of the most significant bit B
1
is written to each pixel. Then, after the data has been written, a sustaining discharge pulse is applied to the entire panel to allow only those pixels to which the data has been written to emit light for display. Subsequently, the sub-fields SF
2
and other sub-fields are also driven in the same way. To provide sufficient brightness, for example, the pulse is applied to the sub-field SF
1
256 times, to the sub-field SF
2
128 times, and to sub-fields SF
3
to SF
8
64 times, 32 times, 16 times, 8 times, 4 times, and 2 times during the sustaining discharge period of each of the sub-fields. The numerals in
FIG. 1
designate a weight assigned to each of the sub-field.
The aforementioned arrangement, in which one field is constituted so that the relative ratio of brightness decreases with time, is called a descending-order sub-field arrangement. In contrast, an arrangement in which one field is constituted so that the relative ratio of brightness increases with time is called an ascending-or der sub-field arrangement. These arrangements practiced in the sub-field technique are not special ones but have been conventionally used in general.
Other than these two arrangements, there are also other various techniques available only if the techniques are intended to display gradation. However, in cases where arrangements were simply replaced with one another in these sub-field arrangements, any one of the arrangements would cause the following disadvantages.
In general, the update speed of a screen is so set as to be the same as that of the vertical synchronizing signal in both a CRT display and a plasma display device. Accordingly, the optical stimulus to which human eyes are actually subjected on the screen is recognized as blinking in brightness proportional to the vertical synchronizing signal. As the repeated cycle of the blinking in brightness becomes longer, the blinking is recognized as more distinct flashing. On the other hand, as the repeated cycle becomes shorter, the blinking is recognized as continuous lighting. The boundary cycle between the continuous lighting and the flashing is called the “CFF (Critical Fusion Frequency or Critical Flicker Frequency)”. The CFF is described in a paper, “Gradation Display Scheme for Television using a memory gas-discharge panel”, by Kohgami and Mikoshiba, which is described on pages 11 to 13 of Shingaku Engineering report EID 90-9.
The vertical synchronizing frequency employed by the European TV standards is 50 Hz in general. Thus, the repeating cycle of the vertical synchronizing signal and that of the video signal are generally the same as the CFF or 20 msec. Recognition of blinking in brightness as flashing or continuous lighting depends on the brightness level of a video signal to be displayed. One would recognize a similar video signal displayed more frequently as flashing if the signal had a higher brightness level. A state that is recognized as flashing is generally called a flicker. A flicker, recognized on the whole screen and caused by a low vertical synchronizing frequency, is called a large-area flicker. The large-area flicker frequently causes a problem of interfering with viewing of the screen on which signals are displayed particularly with high brightness levels.
As countermeasures against such a large-area flicker, a technique called the “100 Hz TV” for increasing the vertical frequency two times at the reception side of images has been used lately in the television with a CRT. This technique can be realized by accumulating image data for one picture in a memory and reading out the data twice at double speed. This technique can reduce the large-area flicker to such an extent that the flicker is hardly detected.
It is known in the plasma display device that some of the higher order sub-fields can be divided into halves and the arrangement of the two divided sub-field groups can be set as appropriate, thereby reducing the large-area flicker. For example, the aforementioned technique was suggested as processing for increasing the field frequency two times or more to reduce jerkiness in Japanese Patent Laid-Open Publication No. Hei 5-127612. Techniques similar to this were suggested in Japanese Patent Laid-Open Publications No. Hei 5-127613, No. Hei 5-127614, and No. Hei 5-127636. Among the publications, the techniques described in Japanese Patent Laid-Open Publications No. Hei 5-127614 and No. Hei 5-127636 aim to reduce flicker.
The higher the brightness is, the more noticeable the large-area flicker becomes. Thus, it is not always necessary to divide all gradation bits into halves in a plasma display device. That is, it is not sufficiently effective to divide lower order bits into halves that contribute to gradation display with low brightness when the large-area flicker is to be reduced. Thus, it is conceivable to divide relatively higher order bits into halves to reduce the large-area flicker. It is described in the aforementioned publications to divide higher order bits into halves in order to reduce the jerkiness of dynamic images. As such, these publications do not aim to reduce flicker. Accordingly, no publications are available so far that disclose the number of bits, settings of time, and arrangements to be divided into. Therefore, it cannot be said that the techniques set forth in the publications sufficiently and effectively prevent the large-screen flicker even when the techniques are carried out as they are describ
Kovalick Vincent E.
McGinn & Gibb PLLC
NEC Corporation
Shalwala Bipin
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