Synchronous delay circuit and semiconductor integrated...

Details Synchronous delay circuit and semiconductor integrated... Synchronous delay circuit and semiconductor integrated...

2001-03-05

2003-01-21

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S270000

Reexamination Certificate

active

06509775

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a clock control technique for a semiconductor integrated circuit and, more particularly, to a synchronous delay circuit for controlling clock signals and to a semiconductor integrated circuit apparatus having such synchronous delay circuit.
BACKGROUND OF THE INVENTION
A synchronous delay circuit for eliminating clock skew within a short synchronous time period has come to be used in the high-speed clock synchronization circuit because of its simplified circuit structure and only low power consumption. For this sort of the synchronous delay circuit, reference may be had e.g., to the following publications:
[1] JP Patent Kokai JP-A-8-237091;
[2] JP Patent Kokai JP-A-11-73238 (U.S. Pat. No. 6,075,395);
[3] Jin-Man Han et al., Skew Minimization Technique for 256M-bit Synchronous DRAM and Beyond, 1996 Symp. on VLSI Circ. pp. 192-193;
[4] Richard B. Watson et al., Clock Buffer Chip with Absolute Delay Regulation Over Pricrss and Environment Variations, Proc. of IEEE 1992 CICC (Custom Integrated Circuits Conference), 25.2;
[5] Yoshihiro OKAJIMA et al., Digital Delay locked Loop and Design Technique for High-Speed Synchronous Interface, IEICE TRANS. ELECTRON., Vol. E79-C, No. 6, June 1996, pp. 798-807.
FIG. 5
shows an illustrative structure of a semiconductor integrated circuit having a conventional synchronous delay circuit. Meanwhile, the structure shown in
FIG. 5
is based on the structure of the synchronous delay circuit described in the publication [2] (JP-A-11-73238) filed by the same applicant.
A synchronous delay circuit
100
includes, as its basic structure, a first delay circuit delay circuit chain
11
for period (delay) measurement, adapted for Propagation of clock Pulses or clock Pulse edges therein, and a second delay circuit chain
12
for delay reproduction, capable of propagation of pulses or pulse edges by a length corresponding to a length of the propagation of the pulse or pulse edges through the first delay circuit chain
11
.
The configuration shown in
FIG. 5
is designed so that the clock period tCK of the input clocks
3
less the delay tCTS of a clock tree
4
, as detected by a delay detection circuit
5
as later explained, or tCK−tCTS, is measured by the synchronous delay circuit
100
, in consideration of fluctuations in the propagation delay time of the clock tree
4
, to realize clocks substantially free of skew with respect to input clocks
4
even if the propagation delay time tCTS of the clock tree
4
is changed.
In designing a semiconductor integrated circuit, there is used e.g., the designing by the clock tree synthesis (CTS) method of optimally introducing a buffer for equalizing the delay in the clock signal wiring network to provide a tree-like layout, in order to minimize the difference in clock signal delay time, in such a manner as to distribute clock signals in respective clock using circuits, such as flipflops. The clock tree
4
is made up of clock wiring routes laid out in a tree fashion. In
FIG. 5
, a triangular symbol of the clock tree
4
schematically denotes a buffer inserted in the clock tree for equalizing the delay in driving the load. It should be noted that the clock tree
4
is shown only schematically such that the number of stages of the buffer circuits comprehended in the clock tree
4
is not necessarily limited to four. In
FIG. 5
, A denotes an input node of the clock tree
4
and B a preset output node, such as a maximum delay node, as selected as a control object in the clock tree
4
. Meanwhile, the clock propagation Path arranged in the clock tree
4
might be any suitable clock signal-wiring route in a semiconductor integrated circuit, without being limited to the signal-wiring path for clock propagation by e.g., the CTS wiring method.
Referring to
FIG. 5
, showing a semiconductor integrated circuit apparatus, when an input clock
3
(IN), fed from e.g., a clock driver, not shown, is fed through a changeover unit
10
to an input node A of a clock tree
4
, a delay detection circuit for inputting the clock signal to its first input terminal resets or inactivates its output D (also termed a monitoring signal), with the delay circuit chain
11
then halting the propagation of the clock signals.
When the clocks fed to a node A of the clock tree
4
reaches the node B after the propagation delay time tCTS, the delay detection circuit
5
. fed with the clock signals in its second input terminal, sets (activates) its output D and, responsive to this output D, the delay circuit chain
11
permits the clock propagation.
FIG. 6
shows an illustrative structure of a synchronous delay circuit
100
and the delay detection circuit
5
shown in FIG.
5
. Referring to
FIG. 6
, the synchronous delay circuit
100
includes a first delay circuit chain
11
made up of plural unit delay elements, for transmitting pulses or pulse edges of input clocks (IN) and for issuing an output at an arbitrary position of the transmission path, a second delay circuit chain
12
, similarly made up of plural unit delay devices, for being fed at an arbitrary position of the transmission path with clock Pulses and pulse edges for transmission, and a control circuit array
18
, made up of plural control circuits, each having a signal input terminal, a signal output terminal and an input/output control terminal. The first and second delay circuit chains
11
,
12
are designed so that the respective signal transmission paths are reversed in the signal propagation direction to each other. Moreover, the first delay circuit chain
11
and the second delay circuit chain
12
are interconnected through the control circuit array
18
so that the sides of the first delay circuit chain
11
closer to an input end of clocks IN are connected to the sides of the second delay circuit chain
12
closer to an output end of the clocks, and so that, at a time point when the clock signal input to the first delay circuit chain
11
has propagated a preset time as from the time point of inputting of the signal to the first delay circuit chain
11
that is at a time point when the next clock signal is input, a signal is input to the input/output control terminal of the control circuit array
18
at a position to which the clock signal has propagated so that the clock signal propagating through the first delay circuit chain
11
is input and transferred into the second delay circuit chain
12
from the Position corresponding to the propagated (traversed) position.
In the embodiment shown in
FIG. 6
, the delay circuit chain
11
for delay measurement and the delay circuit chain
12
for delay reproduction (reconstruction) are arranged in reverse directions to each other. Of course, the present invention is not limited to this configuration. A pair of delay circuit chains through which signal propagation occurs in the same direction may also form the synchronous delay circuit in the known manner. Reference may be had to the above-mentioned publications for alternative construct ions of the synchronous delay circuit, the entire disclosures thereof being incorporated in the present invention by reference thereto.
In the first delay circuit chain
11
, in which a clock pulse has been input from the input end C, the clock pulse progresses through the inside of the first delay circuit chain
11
and, when a clock pulse next following the propagating clock pulse is input, the control circuit array
18
is activated responsive to this next clock pulse to transfer the clock pulse from the position in the first delay circuit chain
11
through which it is propagating through the control circuit array
18
registering with this position to the second delay circuit chain
12
. The clock Pulse transferred to the second delay circuit chain
12
progresses through the second delay circuit chain
12
in a reverse direction to the propagating direction of the clock pulse through the first delay circuit chain
11
and is issued as output. In the embodiment shown in
FIG. 6

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