Diode structure on MOS wafer

Details Diode structure on MOS wafer Diode structure on MOS wafer

2001-02-27

2002-10-15

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S140000, C257S141000, C257S162000, C711S115000

Reexamination Certificate

active

06465864

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90103093, filed Feb. 13, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a diode structure on a MOS wafer. More particularly, the present invention relates to a diode structure that produces a low parasitic current due to a built-in barrier layer or an oxide layer.
2. Description of Related Art
In general, a voltage (typically, 12V) must be applied to an electrically erasable programmable read only memory (EEPROM) to erase stored data. However, most computer systems demand a driving voltage of only 3.3V or 5V, and hence a 12V supply is rarely supplied. To erase stored data within an EEPROM unit, a step-up circuit is needed to provide the necessary high voltage.
FIG. 1
is a diagram showing a conventional step-up circuit module capable of generating a 12V output.
The voltage step-up circuit
100
shown in
FIG. 1
includes a first transistor
102
, a second transistor
104
, an inductor
106
and a diode
108
. A power voltage VCC of 5V is used. The transistors
102
and
104
are switched by signals S
1
and S
2
sent to their respective gates. When both transistors
102
and
104
are conductive, a current i
L
will flow through the inductor
106
, the first transistor
102
and the second transistor
104
. On the other hand, when any one of the transistors
102
and
104
is closed, the current i
L
will flow via the inductor
106
and the diode
108
. By timing the conductance of the transistors
102
and
104
and selecting appropriate electrical properties for the inductor
106
, a voltage at terminal V
2
higher than the voltage at terminal V
1
can be produced. The voltage at the terminal V
2
can be driven to a voltage (12V) high enough to operate the EEPROM.
In
FIG. 1
, if the diode
108
in the voltage step-up circuit
100
is a discrete component, there are few problems in applications. However, if the diode
108
is fabricated on the same wafer housing other MOS transistors, the power conversion capacity of the step-up circuit
100
may drop.
FIG. 2
is a schematic cross-sectional view of a conventional diode on a MOS wafer. As shown in
FIG. 2
, an n-well
202
is formed in a p-substrate
200
. A p
+
-doped region
204
and an n
+
-doped region
206
are formed within the n-well
202
. The p
+
-doped region serves as the anode of the diode while the n
+
-doped region
206
serves as the cathode of the diode. A p
+
-doped region
208
is also formed in the p-substrate
200
to one side of the n-well
202
. The p
+
-doped region
208
serves as a ground (GND) terminal permitting the flow of a substrate current.
Due to the presence of a parasitic path (p
+
-doped region
204
—n-well
202
—p substrate
200
—p
+
-doped region
208
), a current i flowing in from the anode of the diode into the p
+
-doped region
204
will diverge and produce a current i
D
and a current i
p
. The current i
D
flows via the p
+
-doped region
204
, the n-well
202
, the n
+
-doped region
206
and arrives at the anode of the diode. The current i
p
flows via the parasitic path and arrives at the ground terminal (GND).
However, while the current i
D
is a useful operating current for the diode, the current i
p
is a parasitic current of the MOS wafer representing waste power. Since power conversion efficiency of the voltage step-up circuit depends on the current i
D
, power conversion efficiency will drop in the presence of the parasitic current i
p
. That means, the higher the parasitic current, the lower will be the power conversion capacity of the voltage step-up circuit.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a diode layout structure having a low parasitic current so that power conversion efficiency of a voltage step-up circuit is increased.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a diode layout structure on a silicon wafer. The diode structure includes a substrate, a first ion-doped well, a first ion-doped region, a second ion-doped region, a second ion-doped well and a third ion-doped region. The first ion-doped well is formed in the substrate. The first ion-doped region is formed in the first ion-doped well and the second ion-doped region is formed in the first ion-doped well to one side of the first ion-doped region without touching the first ion-doped region. The second ion-doped well having a circular shape is formed in the substrate surrounding the first ion-doped well without touching the first ion-doped well. The third ion-doped region, also having a circular shape, is formed inside the circular second ion-doped well.
This invention also provides a second type of diode layout structure on a silicon wafer. The diode structure includes a substrate, an oxide layer, a first ion-doped region, a second ion-doped region and a third ion-doped region. The oxide layer is formed over the substrate. The first ion-doped region is formed over the oxide layer. The second ion-doped region is formed over the oxide layer on one side and in contact with the first ion-doped region. The third ion-doped region is formed over the oxide layer on one side and in contact with the second ion-doped region.
This invention also provides a third type of diode layout structure on a silicon wafer. The diode structure includes a substrate, an ion-doped well, a first ion-doped region, a second ion-doped region, a deep-layer ion-doped well and a third ion-doped well. An ion-doped well having a circular shape is formed in the substrate. The first ion-doped region is formed in the substrate within and having no contact with the circular ion-doped well. The second ion-doped region is formed in the substrate to one side of the first ion-doped region. The second ion-doped region has no contact with either the first ion-doped region or the circular ion-doped well. A deep-layer ion-doped well is formed in the substrate underneath but without contact with the first ion-doped region and externally bounded by the circular ion-doped well. The third ion-doped region is formed inside the circular ion-doped well above the deep-layer ion-doped well. Furthermore, the third ion-doped region is in contact with the first ion-doped region, the second ion-doped region, the ion-doped well and the deep-layer ion-doped well.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6104045 (2000-08-01), Forbes et al.
patent: 6108751 (2000-08-01), Lee et al.

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