Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

2001-09-14

2002-10-01

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Multiple values

C365S185220, C365S185240, C365S185300

Reexamination Certificate

active

06459612

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory and particularly relates to an electrically rewritable nonvolatile semiconductor memory (EEPROM, flash memory) employing memory cells each having a stack of a floating gate (charge accumulation layer) and a control gate.
The present invention also relates to a nonvolatile semiconductor memory utilizing a multilevel storage technique.
There is conventionally known, as a nonvolatile semiconductor memory which is electrically rewritable and capable of realizing high integration, an NAND type EEPROM having a plurality of memory cells mutually connected in series.
FIG. 1A
is a plan view showing one NAND cell formed on a memory cell array on an EEPROM chip and
FIG. 1B
is an equivalent circuit thereof.
FIG. 2A
is a cross-sectional view taken along the line
2
A—
2
A of FIG.
1
A.
FIG. 2B
is a cross-sectional view showing one example of a cross section taken along the line
2
B—
2
B of FIG.
1
A and particularly shows a case of employing an LOCOS element isolation film (
312
).
FIG. 3
is a cross-sectional view showing another example of a cross section taken along the line
2
B—
2
B of FIG.
1
A and particularly shows a case of employing a trench element isolation insulating film (
322
). It is noted that a portion surrounded by a dashed line corresponds to the portion shown in FIG.
2
B.
As shown in
FIGS. 1A
,
2
A,
2
B and
3
, a memory cell array consisting of a plurality of NAND cells are formed on a P type silicon substrate (or P type well which will be referred to as herein)
311
surrounded by the element isolation oxide film
312
. One NAND cell includes, for example, eight memory cells MC (MC
1
to MC
8
) mutually connected in series.
Each memory cell MC has a stacked gate structure. The stacked gate structure consists of an insulating film
313
formed on the P type well
311
, a floating gate
314
(
314
1
to
314
8
) formed on the insulating film
313
, an insulating film
315
formed on the floating gate
314
and a control gate (CG)
316
(
316
1
to
316
8
or CG
1
to CG
8
) formed on the insulating film
315
.
An N
+
diffused layer (source/drain region)
319
of one memory cell MC is shared with its adjacent memory cell MC, whereby, for example, eight memory cells MC are connected to one another in series and one NAND cell is formed.
One end of a current path of the NAND cell is connected to a bit line BL (
318
) through a drain-side select gate transistor ST
1
and the other end thereof is connected to a source line SL through a source-side select gate transistor ST
2
.
The gate electrode of each of the select gate transistors ST
1
and ST
2
has a structure in which the floating gate
314
(
314
9
,
314
10
) and the control gate
316
(
316
9
,
316
10
), for example, are electrically connected with each other at a portion which is not shown.
The P type well
311
, on which memory cells MC, the select gate transistors ST
1
, ST
2
and the like are formed, is covered with a CVD oxide film
317
or the like. The bit line (BL)
318
is arranged on the CVD oxide film
317
. The bit line (BL)
318
extends in column direction.
The control gate CG (CG
1
to CG
8
) of each memory cell MC is shared among NAND cells arranged in row direction and functions as a word line WL (WL
1
to WL
8
). The row direction is a direction orthogonal to the column direction.
The gate electrode (
314
9
,
316
9
) of the drain-side select gate transistor ST
1
is shared among drain-side select gate transistors ST
1
arranged in row direction and functions as a drain-side select gate line SGD.
The gate electrode (
314
10
,
316
10
) of the source-side select gate transistor ST
2
is shared among source-side gate transistors ST
2
arranged in row direction and functions as a source-side select gate line SGS.
The data stored by one memory cell MC in the NAND cell is multilevel, i.e., binary or more.
In case of storing binary data, the range of the possible threshold voltages of the memory cells MC is divided into two types which are assigned data “1” and “0”, respectively. In case of the NAND type memory, the threshold voltages after data erase are normally “negative” and defined as, for example, “1”. The threshold voltages after data write are normally “positive” and defined as “0”.
In case of storing multilevel data, e.g., four-level data, the range of the possible threshold voltages of the memory cells MC is divided into four types, which are assigned data “11”, “10”, “01” and “00”, respectively. In case the NAND type memory, the threshold voltages after data erase are normally “negative” and defined as “11”. The threshold voltages after data write are normally “positive” and defined as “10”, “01” and “00” in the order in which threshold voltages are higher.
It is not always necessary that only the data after data erase have “negative” threshold voltages. It suffices that the range of the possible threshold voltages of memory cells MC is divided into a plurality of types. It also suffices that the polarity of a threshold voltage, i.e., whether the threshold voltage is “negative” or “positive”, is opposite to that described above.
In the data write operation technique of such an NAND type EEPROM, a local self boost technique (LSB technique) is recently regarded as a favorable one. The operation of the NAND type EEPROM adopting the LSB technique will be described hereinafter with reference to FIG.
1
B.
(Data Erase Operation)
Data erase is roughly divided into two ways, i.e., batch erase and block erase.
In batch erase, the data of all the memory cells MC existing on the memory cell array are simultaneously erased. In this case, the potentials of all the control gates CG (word lines WL) on the memory cell array are set at 0V, the bit lines BL and the source lines SL are turned into a floating state, respectively and then a high voltage (e.g., 20V) is applied to the P type well
311
. By doing so, electrons are discharged into the P type well
311
from the floating gates
314
of all the memory cells MC existing in the memory cell array and the threshold voltages of all the memory cells MC are shifted in negative direction.
In block erase, the data of the memory cells MC existing on the memory cell array are erased in units of blocks. Normally, one block consists of a group of NAND cells which are arranged in row direction and which share control gates CG (word lines WL). In this case, the potentials of the control gates CG (word lines WL) in a select block are set at 0V, a high voltage (e.g., 20V) is applied to control gates CG (word lines WL) in non-select blocks, the bit lines BL and the source lines SL are turned into a floating state, respectively and a high voltage (e.g., 20V) is applied to the P type well
311
. By doing so, electrons are discharged from the floating gates
314
of the memory cells MC existing in the select block into the P type wall
31
and the threshold voltages of the memory cells MC in the select block are shifted in negative direction.
The above-stated data erase operation is executed prior to the data write operation to be conducted to the entire memory cell array or the data write operation to be conducted in block units.
(Data Write Operation (LSB technique))
Before starting the description of the data write operation, it is assumed that a select control gate CG in the select block is “CG
2
(word line WL
2
)”.
In the data write operation, a predetermined positive voltage Vsgd is applied to a select gate line SGD in a select block and 0V is applied to a select gate line SGS. Also, 0V is applied to all word lines WL and all select gate lines SGD and SGS in non-select blocks.
In this state, if data write is carried out by means of the LSB technique, the select word line WL
2
is applied with a high voltage Vpp for data write, non-select word lines WL
1
and WL
3
adjacent to the select word line WL
2
are applied with 0V, respectively, and non-select word lines WL
4
to WL
8
other than the non-select word lines WL
1
and WL
3
are applied with a voltag

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