Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-10-16
2002-10-08
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S501000, C257S508000, C257S621000, C257S758000, C257S773000
Reexamination Certificate
active
06462395
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and, more particularly, to a semiconductor device having a multilayer interconnection structure.
2. Description of the Related Art
The number of active elements in recent ultra-fine semiconductor integrated circuits have greatly increased. To interconnect those numerous active elements, a first wiring layer is covered with an interlayer insulating film, and a second wiring layer is formed on the interlayer insulating film. A conductive plug is then formed in the interlayer insulating film so as to connect the first and second wiring layers. This structure is called a multilayer interconnection structure.
FIG. 1
shows the structure of a conventional semiconductor device
10
having a multilayer interconnection structure.
As shown in
FIG. 1
, the semiconductor device
10
is formed on a Si substrate
11
provided with isolation areas
11
A and
11
B. The isolation areas
11
A and
11
B define an active region on the Si substrate
11
, and diffusion areas
11
a
and
11
b
acting as source and drain of a MOS transistor are formed in the active region.
On the Si substrate
11
, a gate insulating film
12
a
is formed to cover a channel region formed between the diffusion areas
11
a
and
11
b,
and a gate electrode
12
b
is formed on the gate insulating film
12
a.
In
FIG. 1
, sidewall insulating films
12
c
and
12
d
are further formed on both side surfaces of the gate electrode
12
b.
The gate insulating film
12
a,
the gate electrode
12
b,
and the sidewall insulating films
12
c
and
12
d
constitute a gate structure of the MOS transistor. In the figure, the gate electrode
12
b
has a polycide structure, having a silicide layer formed on a polysilicon pattern, as indicated by a dotted area in the figure.
On the Si substrate
11
, a first interlayer insulating film
13
is formed to cover the gate electrode
12
b
and the sidewall insulating films
12
c
and
12
d.
In the first interlayer insulating film
13
, contact holes
13
a
and
13
b
are formed to expose the diffusion areas
11
a
and
11
b.
A first-layer wiring pattern
14
a
to be electrically in contact with the diffusion area
11
a
through the contact hole
13
a
is formed on the first interlayer insulting film
13
. Another first-layer wiring pattern
14
b
to be electrically in contact with the diffusion area
11
b
through the contact hole
13
b
is also formed on the first interlayer insulating film
13
. Here, a conductive plug
14
p
extends from the wiring pattern
14
a
through the contact hole
13
a,
while a conductive plug
14
q
extends from the wiring pattern
14
b
through the contact hole
13
b.
The wiring pattern
14
b
may be a contact pad to make electric contact with the diffusion area
11
b.
On the first interlayer insulating film
13
, a second interlayer insulating film
15
is formed to cover the wiring patterns
14
a
and
14
b.
In the second interlayer insulating film
15
, a contact hole
15
a
that penetrates through the first interlayer insulating film
13
is formed to expose the gate electrode
12
b.
On the second interlayer insulating film
15
, a second-layer wiring pattern
16
is formed to make electric contact with the gate electrode
12
b
through the contact hole
15
a.
A third interlayer insulating film
17
to cover the wiring pattern
16
is further formed on the second interlayer insulating film
15
. Here, a conductive plug
16
p
extends from the wiring pattern
16
through the contact hole
15
a.
In the third interlayer insulating film
17
, contact holes
17
a
and
17
b
are formed to expose the wiring patterns
14
a
and
14
b,
respectively. The wiring pattern
16
may be a contact pad to make electric contact with the gate electrode
12
b.
On the third interlayer insulating film
17
, third-layer wiring patterns
18
a
and
18
b
are formed to make contact with the wiring pattern
14
a
through the contact hole
17
a
and with the wiring pattern
14
b
through the contact hole
17
b,
respectively. On the third interlayer insulating film
17
, a fourth interlayer insulating film
19
is further formed to cover the wiring patterns
18
a
and
18
b.
Here, a conductive plug
18
p
extends from the wiring pattern
18
a
through the contact hole
17
a,
and a conductive plug
18
q
extends from the wiring pattern
18
b
through the contact hole
17
b.
In the fourth interlayer insulating film
19
, a contact hole
19
a
is formed to expose the wiring pattern
16
. The contact hole
19
a
is covered with a conductive plug
20
to make electric contact with the wiring pattern
16
.
With the above structure, the wiring pattern can be simplified, compared with the wiring pattern formed by a single wiring layer or two wiring layers. Accordingly, signal delay, which is often caused in a large scale semiconductor integrated circuit comprising a semiconductor device having an ultra-fine structure, is reduced. Also, more freedom is allowed in the design of the wiring pattern in such a large scale semiconductor integrated circuit.
In the conventional semiconductor device
10
shown in
FIG. 1
, however, there is the problem of contact resistance at the connecting portion between a conductive plug and the wiring pattern directly below the conductive plug. For instance, the wiring pattern
14
b
and the wiring pattern
18
b
are connected by a conductive plug that fills the contact hole
17
b
in the interlayer insulating film
17
. The diameter of the contact hole
17
b
is substantially uniform and generally smaller than the width of the wiring pattern
14
b,
resulting in the contact resistance. The smaller the diameter of a contact hole, the greater the contact resistance. Accordingly, the contact resistance is a very serious problem in today's semiconductor devices having an ultra-fine structure, which is so-called called submicron or sub-quarter-micron.
Furthermore, in the conventional semiconductor device
10
shown in
FIG. 1
, the diameter of the contact hole
17
b
is small. If the contact hole
17
b
deviates from a predetermined location in a photolithographic process, the contact area between the conductive plug and the wiring pattern
14
b
becomes even smaller, resulting in greater contact resistance. As the contact resistance increases, the time constant of the entire multilayer interconnection structure becomes greater. With the greater time constant, it is difficult to minimize signal delay.
SUMMARY OF THE INVENTION
A general object of the present invention is to provide semiconductor devices and semiconductor device production methods in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a semiconductor device having a multilayer interconnection structure that reduces contact resistance between wiring layers, and a method of producing such a semiconductor device.
Another specific objects of the present invention is to provide a semiconductor device having a multilayer interconnection structure that prevents an increase of contact resistance even if a contact hole deviates from a predetermined location, and a method of producing such a semiconductor device.
The above objects of the present invention are achieved by a semiconductor device having a multilayer interconnection structure, comprising: a first-layer wiring pattern; an interlayer insulating film formed on the first-layer wiring pattern; a second-layer wiring pattern formed on the interlayer insulating film; and a conductive plug that is formed in the interlayer insulating film and connects the first-layer wiring pattern and the second-layer wiring pattern. The conductive plug comprises: a contact portion that contacts with the first-layer wiring pattern; and a connecting portion that extends from the contact portion toward the second-layer wiring pattern. The contact portion has a larger area than the connecting portion.
The above objects of the present invention are also achieved by a method of producing
Fukuda Masatoshi
Katata Tomio
Nakamura Naofumi
Suzuki Toshiya
Armstrong Westerman & Hattori, LLP
Flynn Nathan J.
Forde Remmon R.
Fujitsu Limited
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