Self-testing digital circuits

Details Self-testing digital circuits Self-testing digital circuits

1983-06-20

1985-11-05

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

045518386

ABSTRACT:
In order to test a digital circuit, such as a digital logic circuit (e.g., 100), for faults, during the first three cycles of a test operation of many cycles in duration, a predetermined input word is delivered to the input terminals of the logic circuit. Throughout the remaining cycles of the test operation, each output terminal of the circuit is connected by an input multiplexer (e.g., 200) to a fixed different one (or more) of the input terminals, whereby output of each cycle serves as input for the next cycle of the test operation. A counter (e.g., 300) counts the number of test operation cycles and sends an enabling signal to a signature detector (e.g., 400) when the counter counts a predetermined number of test cycles. Finally, in response to this enabling signal, each output terminal's output bit developed during the last cycle of the test operation is compared by the signature detector (e.g., 400) with the corresponding "correct" bit. Any discrepancy between any such output bit and the corresponding expected fault-free bit indicates at least one fault in the circuit.

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Bottorf et al., Self-Testing Scheme Using Shift Register Latches, IBM Tech. Discl. Bulletin, vol. 25, No. 10, Mar. 1983, pp. 4958-4960.
Z. Barzilai et al., "Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing," IEEE Transactions on Computers, vol. C-32, No. 2, Feb. 1983, pp. 190-194.

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