Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-11-30
2002-10-08
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06463452
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a digital value processor for estimating the square of a digital value, to a corresponding method and to a mean signal power estimating device using such a digital value processor.
BACKGROUND
In digital communication systems, a digital signal needs to be analog modulated before being forwarded to a transmitter for transmission. If it is desired to monitor the output power of the transmitter, the straightforward solution consists in measuring the analog signal. However, if it is desired to measure or estimate the output power of the transmitter on the basis of the digital signal, then this can be done by monitoring the squares of the values contained in the digital signal. For example, a CDMA (code division multiple access) signal contains so called weighted chips, such that said weighted chips are an example of digital values contained in a digital signal, and a monitoring of the squares of the in-phase and quadrature phase components of the weighted chips gives an indication of the transmitter output power of the transmitter sending out said CDMA digital signal.
Consequently, in order to estimate the power of a digital signal, a means for calculating squares of digital values is required. The basic operation of multiplying a number by itself is well-known. A large number of numeric methods is known for achieving such a multiplication. Furthermore, different methods of subsampling an input stream prior to a possible power estimation are known. Algorithms based on the above described concepts are implemented in many devices, e.g. in digital signal processors.
For example, DE 40 33 507 C2 shows a circuit arrangement for the digital multiplication of integer numbers. The basic operation described in this document consists in first calculating a logarithm, then performing an adding operation, and then the operation that is inverse to calculating the logarithm. It is mentioned that the calculation of the logarithm and the inverse operation can be accelerated by using a mathematic approximation of the exponential curve. In accordance with this document, a coding unit for calculating the logarithm linearly approximates an exponential curve piece by piece in such a way that the number of linear sections is at least equal to the bit number of the respective integer number. In connection with this linear approximation, document DE 40 33 507 C2 proposes an operation based on a complicated truth table. This document however does not specifically address the calculation of squares.
There are also methods for calculating a square-root of a sum of squares, e.g. disclosed in EP 0 811 909 A1, or for estimating a mean square value, e.g. disclosed in EP 0 205 351 A1. However, eventhough these methods relate to the calculation of a term that analytically would require the calculation of a square, both methods avoid actually calculating the square of a digital value.
OBJECT OF THE INVENTION
The object of the present application is to provide a digital value processor and digital value processing method for estimating the square of a digital value that can be implemented in a simple way, i.e. with little hardware expenditure and without complicated processing steps.
SUMMARY OF THE INVENTION
This object is solved by a digital value processor according to claim 1and a digital value processing method according to claim 14. Preferably, the digital value processing according to the invention is applied to the estimation of the mean output power of a digital signal.
The basic concept of the invention consists in using powers of 2 for calculating the square of the digital value x
a
, in the sense that powers of 2 are used as anchor points for a linear approximation of the square function y=x
2
. More specifically, first the two integer powers of 2 between which x
a
lies, i.e.
2
i
≦x
a
<2
i+1
(1)
are determined. Then2
i
is used as a first processing value and (3x
a
−2
i+1
) is used as a second processing value for calculating an estimate&xgr;
a
2
.
By basing the estimation of the square of a digital value, which is a binary number, on integer powers of 2 in the above described way, it is possible to perform all calculations by shift operations and add operations, which leads to simple processing steps and enables very simple processing hardware.
According to a preferred embodiment, the estimate&xgr;
a
2
is calculated as the product of the first and second processing value, i.e.
&xgr;
a
2
=2
i
·(3
x
a
−2
i+1
) (2)
This corresponds to calculating the estimate&xgr;
a
2
by linear interpolation between integer powers of 2 as anchor points, as shown in FIG.
5
. This will be explained in more detail later. The calculation of the estimate can then preferably be performed only by left shift operations and add operations. According to another preferred embodiment, in which the average estimation error is reduced, the estimate&xgr;
a
2
is calculated by additionally performing a truncating operation, i.e.
&xgr;
a
2
=2
i
·2
i−Q
·└(3
x
a
−2
i+1
)/2
i−Q
┘ (3),
where└x┘ means the integer part of a real number x, i.e. the truncation operation. In this way the average estimation error is reduced. Preferably the calculation operation is performed only by left and right shift operations and add operations.
Due to the fact that the magnitude of the estimation error in the above described approximation on the basis of integer powers of 2 increases for large digital values, the device and method of the invention are preferably applied to such digital signals where the occurrence of large magnitudes is less probable. This will typically be the case for digital signals that have been generated in accordance with a constraint on the maximum output power for the analog transmitter.
REFERENCES:
patent: 4787056 (1988-11-01), Dieterich
patent: RE35365 (1996-10-01), Colavin
patent: 5629885 (1997-05-01), Pirson et al.
patent: 6298368 (2001-10-01), Miller, Jr.
patent: 6301598 (2001-10-01), Dierke et al.
patent: 30 30 147 (1982-02-01), None
patent: 0 652 507 (1995-05-01), None
patent: 2 236 608 (1991-04-01), None
Burns Doane Swecker & Mathis L.L.P.
Mai Tan V.
Telefonaktiebolaget LM Ericsson
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