Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-07-31
2002-12-03
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S143000, C341S159000
Reexamination Certificate
active
06489910
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an over sampling circuit for interpolating input data discretely and a digital-to-analog converter to which the oversampling circuit is applied. In this specification, it is assumed that a case where function values have finite values except zero in a local region and become zero in regions different from the region is called a “local support.”
BACKGROUND ART
A recent digital audio apparatus, for example, a CD (Compact Disk) player, uses a D/A (digital-to-analog) converter to which an over-sampling technique is applied to obtain a continuous analog audio signal from discrete music data (digital data). Such a D/A converter generally uses a digital filter to raise a pseudo sampling frequency by interpolating input digital data, and outputs smooth analog audio signals by passing each interpolation value through a low-pass filter after generating a staircase signal waveform with each interpolation value held by the sample holding circuit.
A data interpolation system disclosed in WO99/38090 is well known as a method of interpolating data into discrete digital data. In this data interpolation system, differentiation can be performed only once in the whole range, and a sampling function is used such that two sampling points each before and after an interpolation point, that is, a total of four sampling points, can be considered. Since the sampling function has values of a local support unlike the sinc function defined by sin (&pgr;ft)/(&pgr;ft) where f indicates a sampling frequency, there is a merit that no truncation errors occur although only four pieces of digital data are used in the interpolating operation.
Generally, oversampling is performed by using a digital filter in which the waveform data of the above mentioned sampling function is set to a tap coefficient of an FIR (finite impulse response) filter.
If the oversampling technology of performing an interpolating operation for discrete digital data using the above mentioned digital filter, a low pass filter having a moderate attenuation characteristic can be used. Therefore, the phase characteristic with a low pass filter can approach a linear phase characteristic, and the sampling aliasing noise can be reduced. These effects are more outstanding with a higher oversampling frequency. However, if the sampling frequency becomes higher, the number of taps of the digital filter is also increased. As a result, there arises the problem of a larger circuit. In addition, the performance of the delay circuit or multiplier comprises the digital filter is also sped up. Therefore, it is necessary to use expensive parts appropriate for the quick performance, thereby increasing the cost of the required parts. Especially, when the oversampling process is performed using a digital filter, an actual value of a sampling function is used as a tap coefficient. Therefore, the configuration of a multiplier is complicated, and the cost of the parts furthermore increases.
Moreover, although a digital-to-analog converter can be configured by connecting a low pass filter after the oversampling circuit, the above mentioned various problems with the conventional oversampling circuit have also occurred with the digital-to-analog converter configured using the circuit.
BRIEF SUMMARY OF THE INVENTION
The present invention has been achieved to solve the above mentioned problems, and aims at providing an over sampling circuit and a digital-to-analog converter having a smaller circuit at a lower cost of parts.
In an oversampling circuit according to the present invention, a plurality of step function generation unit generate a step function corresponding to each of plural pieces of digital data input at predetermined intervals in synchronization with the input timing of the digital data. After each of a plurality of integrating unit performs digital integration plural times on the data having the value of each step function, addition unit performs an adding operation. Thus, by adding up results of digital integration operations performed after generating a step function corresponding to each of input digital data, output data can be obtained with the values smoothly changing. When the frequency of oversampling is to be set high, it is necessary only to speed up the digital integration operation without the conventional complicated configuration, thereby simplifying the configuration and reducing the costs of parts. Especially, since reset unit resets the operation of the integrating unit at a predetermined timing, it prevents an error generated by an integrating operation, etc. from being accumulated.
Furthermore, each value of the above mentioned step functions is desired to correspond to each of the values of step functions obtained by differentiating plural times piecewise polynomials for a predetermined sampling function configured by the piecewise polynomials. That is, by integrating plural times the above mentioned step function, a waveform corresponding to the predetermined sampling function can be obtained. Therefore, a convolutional operation using a sampling function can be equivalently realized by generating a step function. As a result, the contents of the entire process can be simplified, and the amount of necessary processes for the oversampling process can be reduced.
In addition, the above mentioned step function is desired to equally set the positive and negative areas. Thus, the divergence of integration results of the integrating unit can be prevented.
Furthermore, it is desirable that the above mentioned sampling function has a value of local support with the whole range differentiable only once. It is assumed that a natural phenomenon can be approximated if the whole range is differentiable only once. By setting a smaller number of times of differentiation, the times of the digital integration performed by the integrating unit can be reduced, thereby successfully simplifying the configuration.
In addition, it is desirable that the resetting operation by the reset unit is performed at timing when the value of the sampling function is 0, and is more desirable that the operation is performed at timing when the value of a sampling function of local support converges into 0 while maintaining the differentiability. In the position where the value of the sampling function is 0, since the integration result by each integrating unit can also be 0 theoretically, the operation of each integrating unit can be reset at this timing without influence on the oversampling process, and with error prevented from being accumulated. Furthermore, at the timing (at both ends of sampling function) when a sampling function of local support converges into 0 while maintaining the differentiability, the values are theoretically 0 in all digital integration operations performed plural times. Therefore, each operation of the digital integration can be separately reset, thereby further preventing the accumulation of errors.
Additionally, it is further desirable that the above mentioned step function contains an area of eight sectional areas of equal width weighted by −1, +3, +5, −7, −7, +5, +3, and −1 in a predetermined range corresponding to five pieces of digital data arranged at equal intervals, and that every two of the eight weight coefficients correspond to the input intervals of the digital data. Since simple weight coefficients represented by integers can be used, the mechanism of generating a step function can be simplified.
In addition, it is desirable that the digital integration can be performed two times, and the data can be output from the integrating unit with the value changing like a quadric. To smoothly interpolating plural pieces of discrete data, it is necessary at least to change a value like a quadric. Since it can be realized only by setting the number of times of the digital integration to 2, the configuration of the integrating unit can be simplified.
Furthermore, the digital integration performed by the integrating unit is a process of accumulating
Dellett and Walters
Jean-Pierre Peguy
Sakai Yasue
LandOfFree
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