Processor development systems

Details Processor development systems Processor development systems

1999-03-05

2002-10-29

Jones, Hugh M. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Emulation

In-circuit emulator

C714S733000, C714S727000, C714S726000, C714S030000

Reexamination Certificate

active

06473727

ABSTRACT:

The present invention relates to a method and apparatus for carrying out debugging procedures on a processor, for example a microprocessor, Digital Signal Processing (DSP) processor, or programmable ASIC core.
Software debugging is commonly carried out using In Circuit Emulation (ICE) wherein a monitor program located in the microprocessor provides information to an external host.
It has been recognised that software debugging using ICE techniques may be carried out more expeditiously using techniques adapted from production testing of microprocessor with production scan-chains. Such production scan chains are to be distinguished from boundary scan registers as in the known JTAG standards. In production scan chains, registers are provided through the processor so that the working of a software routine through the processor can be observed, i.e. it is “visible”. For production testing the production scan chain of registers can be loaded with a random pattern of logic values. One or more machine cycles may then be executed, and the logic values are fed into the microprocessor logic. The resultant logic values in the registers may then be uploaded and examined to assess whether the microprocessor logic is working correctly.
A scan module coupled to an ASIC core is commonly used to detect an appropriate time to halt the core's operation, so that off-chip external host can both examine and alter the core's state under the control of user. This is achieved by stopping the system clock, scanning-out the state of the core, modifying the register values in the off-chip host and finally scanning the new state back in. The method essentially gives full observability and controllability of the core by serially accessing every flip-flop in the design.
A key requirement of an embedded debug system for a microprocessor core is to provide access to system memory. It is not commercially viable to make a significant block of memory scannable, so an alternative approach must be found. A known approach to accessing synchronous SRAM for embedded debug purposes makes use of a “monitor” program actually running on the core (target processor). On reaching an appropriate breakpoint, the monitor code is executed and memory values are transferred to and from the core in real time via a memory-mapped mailbox, implemented as a dual-port RAM. It is usual for a software-driven handshaking protocol to be used to control the operation. On completion of the debugger activities, the monitor program is exited and control passes back to the breakpointed program.
The disadvantages with this approach are: firstly, the “monitor” program consumes some significant area of memory in the processor that either raises cost in production devices or means production devices are implemented without debug circuitry. Secondly, the interface between the microprocessor and the mailbox is typically implemented as a parallel bus consuming a considerable number of pins and again raising costs. Thirdly, the only registers “visible” to the off-chip debug circuitry are those that can be accessed by actual processor instructions (located in the “monitor” program), i.e. those that form part of the programming model, and therefore a complete picture of the processor is not given.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a processor development system which can access memory without creating undue demands on memory and creating undue delays.
Accordingly, the present invention provides in a first aspect a processor including in-circuit emulation means comprising a plurality of scan-chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan-chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under the control of the processor, the scan-chains being arranged to control the processor for incrementing the address register, and the scan-chains including a data register coupled to the data bus of the memory to read/write data.
In a second aspect, the invention provides a method of in-circuit emulation for a processor comprising:
1) providing in the processor, a plurality of scan-chains of serially connected registers, a first scan-chain including an address register for providing an address to memory, and one of said chains including a processor control register for the controlling of the address register
2) incrementing the contents of the address register a predetermined amount under control of the processor control register; and
3) reading or writing data for the address locations in a data register located in the scan chains.


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