Electric power conversion systems – Current conversion – With voltage multiplication means
Reexamination Certificate
2001-06-19
2002-10-29
Patel, Rajnikant B. (Department: 2838)
Electric power conversion systems
Current conversion
With voltage multiplication means
C327S536000, C365S226000
Reexamination Certificate
active
06473321
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique which can be especially effective when applied to an internal booster circuit in a semiconductor integrated circuit, and more particularly to a technique which can be effectively applied to, for instance an internal booster circuit in a nonvolatile memory in which stored information can be electrically erased.
A flash memory uses as its memory cell a nonvolatile memory element consisting of a MOSFET of a double gate structure having a control gate and a floating gate, wherein the threshold voltage of the MOSFET can be varied and information can be stored by altering the fixed electric charge of the floating gate. In such a flash memory, writing or erasing any content into or out of memory cells requires a high voltage (e.g. ±10 V or more) to vary the threshold voltage by withdrawing (or ejecting) or injecting an electric charge out of or into the floating gate of the nonvolatile memory element. It is usual in a flash memory to generate such a high voltage from an internal booster circuit provided in a memory chip.
Attempts are now under way to lower the source voltages of semiconductor integrated circuits including semiconductor memories. Flash memories are no exception, and such memories operating at lower than previous source voltages, for instance 3.3 V to 1.8 V, have come to be required. There are two types of flash memories, one type using hot electrons for writing into, and using the FN tunnel phenomenon for erasing any content from, memory cells and the other type using the FN tunnel phenomenon for both writing and erasion. The latter, using the FN tunnel phenomenon for both writing and erasion, requires a higher boosted voltage than the former.
In recent years, techniques regarding so-called multi-value memories, in which data of two or more bits are to be stored in a memory cell, have come to be proposed with a view to increasing the memory capacities of flash memories. In such multi-value memories, the threshold voltage is varied stepwise, for instance from 1 V to 2 V, 3 V and so forth and plural-bit information is stored, being matched with each threshold voltage, to control the quantity of electric charges injected into the floating gate. In order to set one memory cell to one of a plurality of threshold voltages and to read out the stored information accurately, it is necessary to provide some differences in potential in the distribution of the multiple threshold voltages, and consequently the overall potential difference in the distribution of threshold voltages becomes greater than for two-value memory cells. As a result, a higher boosted voltage is required in writing and erasion into and out of multi-value memories than in two-value memories.
A conventional voltage booster circuit using an ordinary charge pump involves a problem that the voltage cannot be boosted by no more than five times approximately, and boosting the voltage beyond a certain boosted level would suffer a sudden drop in efficiency, namely the saturation of boosted voltage.
There are two types of conventional charge pumps, a parallel capacity type as shown in
FIG. 16 and a
serial capacity type as shown in FIG.
17
. Of the two types, a parallel capacity type charge pump shown in
FIG. 16
, first as shown in FIG.
16
(A), charges up the capacities by applying a low source voltage Vss, such as a ground potential, to a first terminal (the lower terminal in the diagram) of a capacity C
1
and a source voltage Vcc higher than Vss via a diode D
1
to a second terminal (the upper terminal in the diagram). Then, as shown in FIG.
16
(B), it operates so as to switch the voltage at the first terminal of the capacity C
1
from the source voltage Vss to Vcc in a state wherein the source voltage Vss is applied to a first terminal of the adjoining capacity C
2
.
This results in voltage boosting of the second terminal of the capacity Cl to 2 Vcc and transfer to the charge on the capacity C
1
to the capacity C
2
via a diode D
2
. By repeating such operations to successively transfer charges on capacities, boosted voltages can be obtained, such as from 2 Vcc to 3 Vcc and to 4 Vcc. When the charge on the capacity C
2
is to be transferred to the next stage, precharging for the next charge transfer at the capacity C
1
of the first stage makes possible efficient voltage boosting. However, in a parallel capacity type charge pump, the presence of diodes intervening between the capacities invites a reduction of the transmitted voltages by as much as the voltages of these diodes in the forward direction.
It is conceivable to use switching elements, such as MOSFETs, instead of the diodes here, but also in that case, diode-connected MOSFETs, in which the gate and drain are coupled, the voltage will drop by as much as the threshold voltage. Or where switching MOSs are used, as is evident from
FIG. 16
, the voltage relationship between the source and drain of the switching MOSs is reversed. In other words, the source voltage may become either lower or higher than the drain voltage.
If, in an attempt to avoid it, P channel type switching MOSs are used, their well region will be of an N type, and if a configuration is so designed that the same voltage as in the source region, where the potential is high, be applied to the well region as in usual MOSFETs, when the potential in the drain region rises, the PN junction with the well region will be biased forward to let a current flow. Therefore, P channel type MOSFETs cannot be used. On the other hand, if N channel type switching MOSs are used, the transmitted voltage is reduced by as much as the threshold voltage of the MOSFETs because of their characteristics, and eventually it is difficult to boost the voltage without entailing a voltage drop.
A serial capacity type charge pump, as shown in
FIG. 17
, charges capacities C
1
, C
2
and C
3
in series in the same direction up to the source voltage Vcc with switches S
1
, S
2
and S
3
between the capacities C
1
, C
2
and C
3
kept in an off state as shown in FIG.
17
(A). Then, as shown in FIG.
17
(B), the switches S
1
, S
2
and S
3
between the capacities C
1
, C
2
and C
3
are turned on, and the charge pump is operated so as to switch the voltage of a first terminal (the left side terminal in the diagram) of a first capacity C
1
from the source voltage Vss to Vcc. Then, the voltage of a second terminal of the capacity C
1
will rise to 2 Vcc, and the voltages of second terminals of capacities C
2
and C
3
will rise to 3 Vcc and 4 Vcc as, though the inter-terminal voltages of the capacities C
2
and C
3
are respectively charged source voltages Vcc, the voltage of each first terminal is switched from Vss to the voltage of the second terminal of the adjoining capacity. Thus, boosted voltages are obtained.
However, while it is effective in reducing the capacity size, in a serial capacity charge pump, to use capacities between the well region and the gate region, utilizing the gate oxide film of MOSFET, which is the thinnest among all the capacities, the actual circuit of such a configuration in this case would be such that capacities Cs of PN junction between the well region and the substrate are connected to capacities C
1
, C
2
and C
3
as shown in FIG.
17
. As a result, when switches S
1
, S
2
and S
3
between the capacities C
1
, C
2
and C
3
are turned on, part of the charges on the capacity at the preceding stage is consumed to charge the parasitic capacity Cs of the next stage, and the boosted voltage will be reduced correspondingly.
SUMMARY OF THE INVENTION
According to what the present inventors studied, a multi-value flash memory requires a high voltage of ∓16 V or more for writing into and erasing any content out of memory cells, and it has been revealed that, where the source voltage is 1.8 V, a booster circuit capable of generating a voltage 10 times as high as thee source voltage, or even higher, will be needed.
Then, the inventors thought a high boosted voltage could be generated by combining the aforemention
Ishii Tatsuya
Kishimoto Jiro
Kubono Shoji
Noda Satoshi
Ogino Takashi
Miles & Stockbridge P.C.
Patel Rajnikant B.
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