Microprocessor having plural internal data buses

Details Microprocessor having plural internal data buses Microprocessor having plural internal data buses

1978-09-05

1981-05-05

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 100

Patent

active

042662702

ABSTRACT:
A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses. The provision plural internal data buses permits a greater number of transfers of digital information to occur within the microprocessor during each machine cycle. The result is more efficient microprocessor operation and higher throughput.

REFERENCES:
patent: 3810114 (1974-05-01), Yamada et al.
patent: 3813651 (1974-05-01), Yamada
patent: 4003028 (1977-01-01), Bennett et al.
patent: 4041472 (1977-08-01), Shah et al.
patent: 4069510 (1978-01-01), Carlow
patent: 4125901 (1978-11-01), Merrow et al.

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