Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-12-27
2002-10-22
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S758000
Reexamination Certificate
active
06469391
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having an interlayer dielectric film and a method of fabricating the same.
2. Description of the Prior Art
In recent years, wires must be refined and multi-layered in order to further increase the degree of integration of a semiconductor integrated circuit. In order to multi-layer the wires, an interlayer dielectric film is provided between the wires. If the surface of the interlayer dielectric film is not flat, steps result in the wires formed on the interlayer dielectric film. Thus, the wires may disadvantageously be disconnected.
Therefore, the surface of the interlayer dielectric film (i.e., the surface of a device) must be rendered as flat as possible. The technique of flattening the surface of the device, referred to as planarization, is increasingly becoming important following refinement and multi-layering of the wires in recent years. An organic SOG (spin on glass) film is known as an interlayer dielectric film frequently employed in planarization. In particular, planarization utilizing flowability of an interlayer dielectric film material is actively developed in recent years.
In order to form the organic SOG film, a solution prepared by dissolving a silicon compound in an organic solvent is dripped on a substrate while rotating the substrate. Thus, a coating of the solution is formed thickly on concave portions of steps defined on the substrate by wires and thinly on convex portions thereof, to relax the steps. Consequently, the surface of the coating of the solution is flattened.
FIGS. 26 and 27
are schematic sectional views for illustrating a process of forming multilevel interconnections of a conventional semiconductor device. A conventional method of forming multilevel interconnections with an interlayer dielectric film of an organic SOG film is now described with reference to
FIGS. 26 and 27
. First, lower wires
101
are first formed, followed by deposition of a silicon oxide film
106
a,
an organic SOG film
104
and a silicon oxide film
106
b,
as shown in FIG.
26
. The silicon oxide film
106
b
is flattened by CMP (chemical mechanical polishing).
Then, contact holes
107
reaching the upper surfaces of the lower wires
101
are formed in the silicon oxide film
106
a,
the organic SOG film
104
and the silicon oxide film
106
b
by general photolithography and anisotropic etching, as shown in
FIG. 27. A
metal material such as tungsten (W), copper (Cu) or aluminum (Al) is formed in the contact holes
107
and on the silicon oxide film
106
b
and part of the metal material located on the silicon oxide film
106
b
is thereafter removed by CMP or etch back, thereby forming contact plugs
103
b.
Thus, multilevel interconnections having excellent flatness can be formed by employing the organic SOG film
104
as part of an interlayer dielectric film.
When employing the organic SOG film
104
as the interlayer dielectric film, however, the contact plugs
103
b
are disadvantageously oxidized or corroded due to moisture and hydroxyl groups discharged from the organic SOG film
104
. Consequently, the electric characteristics of the contact plugs
103
b
are disadvantageously deteriorated.
Further, the organic SOG film
104
discharges gas of moisture etc. into the contact holes
107
when forming the contact plugs
103
b,
to increase the pressures in the contact holes
107
. Thus, flowability of the contact plugs
103
b
is deteriorated to disadvantageously result in defective embedding of the contact plug
103
b.
Consequently, the electric characteristics of the contact plugs
103
b
are disadvantageously reduced.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of preventing a contact plug (conductive member) embedded in an interlayer dielectric film from oxidation and corrosion and keeping the electric characteristics of the conductive member excellent.
Another object of the present invention is to provide a method of fabricating a semiconductor device without discharging gas of moisture etc. into a contact hole (opening) when embedding a conductive member in an interlayer dielectric film.
A semiconductor device according to an aspect of the present invention comprises an interlayer dielectric film, a conductive member embedded in the interlayer dielectric film and a side wall insulator film formed on the side surface of the conductive member.
In the semiconductor device according to the aforementioned aspect, the side wall insulator film formed on the side surface of the conductive member inhibits moisture and hydroxyl groups contained in the interlayer dielectric film from reaching the conductive member. Thus, the conductive member can be prevented from inconvenience such as oxidation or corrosion resulting from moisture and hydroxyl groups discharged from the interlayer dielectric film. Consequently, the electric characteristics of a contact part can be kept excellent.
In the semiconductor device according to the aforementioned aspect, the side wall insulator film preferably contains a material having a function of intercepting moisture and hydroxyl groups. Thus, the side wall insulator film can readily intercept moisture and hydroxyl groups.
In this case, the side wall insulator film preferably includes at least either a silicon oxide film or a silicon nitride film. In this case, further, the silicon oxide film preferably includes a silicon oxide film containing phosphorus and boron added thereto. Thus, the process time for forming the side wall insulator film can be reduced due to the high etching rate of the silicon oxide film containing phosphorus and boron added thereto. Further, the amount of the upper surface of the conductive member as scraped can be reduced due to reduction of the process time for forming the side wall insulator film.
In the semiconductor device according to the aforementioned aspect, the interlayer dielectric film preferably includes an SOG film. Thus, the interlayer dielectric film can be formed with excellent flatness.
In the semiconductor device according to the aforementioned aspect, the interlayer dielectric film preferably includes a coating film containing at least 1 mass % of carbon. When the interlayer dielectric film contains carbon, the mechanical strength of the interlayer dielectric film can be improved. Further, the dielectric constant of the interlayer dielectric film can be reduced. Consequently, parasitic capacitance between multiple wiring layers arranged through the interlayer dielectric film can be reduced.
In the semiconductor device according to the aforementioned aspect, an impurity is preferably introduced into the surface of the interlayer dielectric film. Thus, the portion of the interlayer dielectric film containing the introduced impurity is further improved in mechanical strength, to be capable of preventing a wafer crack resulting from a crack of the interlayer dielectric film caused in a step of polishing the interlayer dielectric film. Further, the portion of the interlayer dielectric film containing the introduced impurity is improved in wettability, to be capable of preventing the surface of the interlayer dielectric film from scratches caused in the step of polishing the interlayer dielectric film.
In the semiconductor device according to the aforementioned aspect, the interlayer dielectric film is preferably formed between a first conductive layer and a second conductive layer, and the first conductive layer and the second conductive layer are preferably electrically connected with each other through the conductive member embedded in the interlayer dielectric film. In this case, the second conductive layer may be formed on the upper surface of the interlayer dielectric film to be in contact with the conductive member. Further, the interlayer dielectric film may include a wiring groove formed on the upper portion of the condu
McDermott & Will & Emery
Sanyo Electric Co,. Ltd.
Wilson Allan R.
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